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XilinxZynq_7000Ddrc



OVP Peripheral Model: XilinxZynq_7000Ddrc



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

Zynq 7000 Platform DDR Memory Controller (DDRC)

Licensing

Open Source Apache 2.0

Limitations

This model implements the full set of registers. There is no behavior included.

Reference

Zynq-7000 TRM (https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf)

Location

The zynq_7000-ddrc peripheral model is located in an Imperas/OVP installation at the VLNV: xilinx.ovpworld.org / peripheral / zynq_7000-ddrc / 1.0.



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table : Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x1000T (True)

Table 1: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_ddrc_ctrl0x032DDRC Control
ab_Two_rank_cfg0x432Two Rank Configuration
ab_HPR_reg0x832HPR Queue control
ab_LPR_reg0xc32LPR Queue control
ab_WR_reg0x1032WR Queue control
ab_DRAM_param_reg00x1432DRAM Parameters 0
ab_DRAM_param_reg10x1832DRAM Parameters 1
ab_DRAM_param_reg20x1c32DRAM Parameters 2
ab_DRAM_param_reg30x2032DRAM Parameters 3
ab_DRAM_param_reg40x2432DRAM Parameters 4
ab_DRAM_init_param0x2832DRAM Initialization Parameters
ab_DRAM_EMR_reg0x2c32DRAM EMR2, EMR3 access
ab_DRAM_EMR_MR_reg0x3032DRAM EMR, MR access
ab_DRAM_burst8_rdwr0x3432DRAM Burst 8 read/write
ab_DRAM_disable_DQ0x3832DRAM Disable DQ
ab_DRAM_addr_map_bank0x3c32Row/Column address bits
ab_DRAM_addr_map_col0x4032Column address bits
ab_DRAM_addr_map_row0x4432Select DRAM row address bits
ab_DRAM_ODT_reg0x4832DRAM ODT control
ab_phy_dbg_reg0x4c32PHY debug
ab_phy_cmd_timeout_rddata_cpt0x5032PHY command time out and read data capture FIFO
ab_mode_sts_reg0x5432Controller operation mode status
ab_DLL_calib0x5832DLL calibration
ab_ODT_delay_hold0x5c32ODT delay and ODT hold
ab_ctrl_reg10x6032Controller 1
ab_ctrl_reg20x6432Controller 2
ab_ctrl_reg30x6832Controller 3
ab_ctrl_reg40x6c32Controller 4
ab_ctrl_reg50x7832Controller register 5
ab_ctrl_reg60x7c32Controller register 6
ab_CHE_REFRESH_TIMER010xa032CHE_REFRESH_TIMER01
ab_CHE_T_ZQ0xa432ZQ parameters
ab_CHE_T_ZQ_Short_Interval_Reg0xa832Misc parameters
ab_deep_pwrdwn_reg0xac32Deep powerdown (LPDDR2)
ab_reg_2c0xb032Training control
ab_reg_2d0xb432Misc Debug
ab_dfi_timing0xb832DFI timing
ab_CHE_ECC_CONTROL_REG_OFFSET0xc432ECC error clear
ab_CHE_CORR_ECC_LOG_REG_OFFSET0xc832ECC error correction
ab_CHE_CORR_ECC_ADDR_REG_OFFSET0xcc32ECC error correction address log
ab_CHE_CORR_ECC_DATA_31_0_REG_OFFSET0xd032ECC error correction data log low
ab_CHE_CORR_ECC_DATA_63_32_REG_OFFSET0xd432ECC error correction data log mid
ab_CHE_CORR_ECC_DATA_71_64_REG_OFFSET0xd832ECC error correction data log high
ab_CHE_UNCORR_ECC_LOG_REG_OFFSET0xdc32ECC unrecoverable error status
ab_CHE_UNCORR_ECC_ADDR_REG_OFFSET0xe032ECC unrecoverable error address
ab_CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET0xe432ECC unrecoverable error data low
ab_CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET0xe832ECC unrecoverable error data middle
ab_CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET0xec32ECC unrecoverable error data high
ab_CHE_ECC_STATS_REG_OFFSET0xf032ECC error count
ab_ECC_scrub0xf432ECC mode/scrub
ab_CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET0xf832ECC data mask low
ab_CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET0xfc32ECC data mask high
ab_phy_rcvr_enable0x11432Phy receiver enable register
ab_PHY_Config00x11832PHY configuration register for data slice 0.
ab_PHY_Config10x11c32PHY configuration register for data slice 1.
ab_PHY_Config20x12032PHY configuration register for data slice 2.
ab_PHY_Config30x12432PHY configuration register for data slice 3.
ab_phy_init_ratio00x12c32PHY init ratio register for data slice 0.
ab_phy_init_ratio10x13032PHY init ratio register for data slice 1.
ab_phy_init_ratio20x13432PHY init ratio register for data slice 2.
ab_phy_init_ratio30x13832PHY init ratio register for data slice 3.
ab_phy_rd_dqs_cfg00x14032PHY read DQS configuration register for data slice 0.
ab_phy_rd_dqs_cfg10x14432PHY read DQS configuration register for data slice 1.
ab_phy_rd_dqs_cfg20x14832PHY read DQS configuration register for data slice 2.
ab_phy_rd_dqs_cfg30x14c32PHY read DQS configuration register for data slice 3.
ab_phy_wr_dqs_cfg00x15432PHY write DQS configuration register for data slice 0.
ab_phy_wr_dqs_cfg10x15832PHY write DQS configuration register for data slice 1.
ab_phy_wr_dqs_cfg20x15c32PHY write DQS configuration register for data slice 2.
ab_phy_wr_dqs_cfg30x16032PHY write DQS configuration register for data slice 3.
ab_phy_we_cfg00x16832PHY FIFO write enable configuration for data slice 0.
ab_phy_we_cfg10x16c32PHY FIFO write enable configuration for data slice 1.
ab_phy_we_cfg20x17032PHY FIFO write enable configuration for data slice 2.
ab_phy_we_cfg30x17432PHY FIFO write enable configuration for data slice 3.
ab_wr_data_slv00x17c32PHY write data slave ratio config for data slice 0.
ab_wr_data_slv10x18032PHY write data slave ratio config for data slice 1.
ab_wr_data_slv20x18432PHY write data slave ratio config for data slice 2.
ab_wr_data_slv30x18832PHY write data slave ratio config for data slice 3.
ab_reg_640x19032Training control 2
ab_reg_650x19432Training control 3
ab_reg69_6a00x1a432Training results for data slice 0.
ab_reg69_6a10x1a832Training results for data slice 1.
ab_reg6c_6d20x1b032Training results for data slice 2.
ab_reg6c_6d30x1b432Training results for data slice 3.
ab_reg6e_7100x1b832Training results (2) for data slice 0.
ab_reg6e_7110x1bc32Training results (2) for data slice 1.
ab_reg6e_7120x1c032Training results (2) for data slice 2.
ab_reg6e_7130x1c432Training results (2) for data slice 3.
ab_phy_dll_sts00x1cc32Slave DLL results for data slice 0.
ab_phy_dll_sts10x1d032Slave DLL results for data slice 1.
ab_phy_dll_sts20x1d432Slave DLL results for data slice 2.
ab_phy_dll_sts30x1d832Slave DLL results for data slice 3.
ab_dll_lock_sts0x1e032DLL Lock Status, read
ab_phy_ctrl_sts0x1e432PHY Control status, read
ab_phy_ctrl_sts_reg20x1e832PHY Control status (2), read
ab_axi_id0x20032ID and revision information page_mask 0x00000204 32 rw 0x00000000 Page mask
ab_axi_priority_wr_port00x20832AXI Priority control for write port 0.
ab_axi_priority_wr_port10x20c32AXI Priority control for write port 1.
ab_axi_priority_wr_port20x21032AXI Priority control for write port 2.
ab_axi_priority_wr_port30x21432AXI Priority control for write port 3.
ab_axi_priority_rd_port00x21832AXI Priority control for read port 0.
ab_axi_priority_rd_port10x21c32AXI Priority control for read port 1.
ab_axi_priority_rd_port20x22032AXI Priority control for read port 2.
ab_axi_priority_rd_port30x22432AXI Priority control for read port 3.
ab_excl_access_cfg00x29432Exclusive access configuration for port 0.
ab_excl_access_cfg10x29832Exclusive access configuration for port 1.
ab_excl_access_cfg20x29c32Exclusive access configuration for port 2.
ab_excl_access_cfg30x2a032Exclusive access configuration for port 3.
ab_mode_reg_read0x2a432Mode register read data
ab_lpddr_ctrl00x2a832LPDDR2 Control 0
ab_lpddr_ctrl10x2ac32LPDDR2 Control 1
ab_lpddr_ctrl20x2b032LPDDR2 Control 2
ab_lpddr_ctrl30x2b432LPDDR2 Control 3



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 2: Publicly available platforms using peripheral 'zynq_7000-ddrc'

Platform NameVendor
Zynq_PSxilinx.ovpworld.org



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