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XilinxZynq_7000Devcfg



OVP Peripheral Model: XilinxZynq_7000Devcfg



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

Zynq 7000 Platform Device Configuration Registers (devcfg)

Licensing

Open Source Apache 2.0

Limitations

This is mainly a register only interface model. It provides behavior to access the power rails using the XADC interface. The power rail data is provided by values stored in memory which can be updated externally. It provides the ability to lock and un-lock registers.

Reference

Zynq-7000 TRM (https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf)

Location

The zynq_7000-devcfg peripheral model is located in an Imperas/OVP installation at the VLNV: xilinx.ovpworld.org / peripheral / zynq_7000-devcfg / 1.0.



Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

NameTypeDescription
boardstringThe XADC interface includes default data values, access is board dependent so must be configured. Valid 'zc706' or 'zc702' (default zc706)
configstringThe configuratation file defining default values and Voltage Monitor names
voutmodeint32Set the value to read for VOUT_MODE (default -12)
statusmfrspecificuns32Set the value to read for STATUS_MFR_SPECIFIC (default 0)



Net Ports

This model has the following net ports:

Table 1: Net Ports

NameTypeMust Be ConnectedDescription
intOutoutputF (False)Interrupt signal
xadcmuxinputF (False)Selects the channel for the XADC interface sample



Bus Master Ports

This model has the following bus master ports:

Bus Master Port: xadc

Table 2: xadc

NameAddress Width (bits)Description
xadc0



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 3: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x1000T (True)

Table 4: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_CTRL0x032Control Register
ab_LOCK0x432LOCK
ab_CFG0x832Configuration Register
ab_INT_STS0xc32Interrupt Status Register
ab_INT_MASK0x1032Interrupt Mask Register
ab_STATUS0x1432Status Register
ab_DMA_SRC_ADDR0x1832DMA Source address Register
ab_DMA_DST_ADDR0x1c32DMA Destination address Register
ab_DMA_SRC_LEN0x2032DMA Source transfer Length Register
ab_DMA_DEST_LEN0x2432DMA Destination transfer Length Register
ab_ROM_SHADOW0x2832ROM_SHADOW
ab_MULTIBOOT_ADDR0x2c32MULTI Boot Addr Pointer Register
ab_UNLOCK0x3432Unlock Register. The boot ROM will unlock the DEVCI by writing 0x757BDF0D to this register.
ab_MCTRL0x8032Miscellaneous control Register PS_VERSION=1 (v2.0 Silicon)
ab_XADCIF_CFG0x10032XADC Interface Configuration Register
ab_XADCIF_INT_STS0x10432XADC Interface Interrupt Status Register
ab_XADCIF_INT_MASK0x10832XADC Interface Interrupt Mask Register
ab_XADCIF_MSTS0x10c32XADC Interface miscellaneous Status Register
ab_XADCIF_CMDFIFO0x11032XADC Interface Command FIFO Register
ab_XADCIF_RDFIFO0x11432XADC Interface Data FIFO Register
ab_XADCIF_MCTL0x11832XADC Interface Miscellaneous Control Register



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 5: Publicly available platforms using peripheral 'zynq_7000-devcfg'

Platform NameVendor
Zynq_PSxilinx.ovpworld.org



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