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XilinxZynq_7000Dmac



OVP Peripheral Model: XilinxZynq_7000Dmac



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

Zynq 7000 Platform DMA Controller (DMAC)

Licensing

Open Source Apache 2.0

Limitations

This model implements the full set of registers. There is no behavior included.

Reference

Zynq-7000 TRM (https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf)

Location

The zynq_7000-dmac peripheral model is located in an Imperas/OVP installation at the VLNV: xilinx.ovpworld.org / peripheral / zynq_7000-dmac / 1.0.



Net Ports

This model has the following net ports:

Table : Net Ports

NameTypeMust Be ConnectedDescription
int0outputF (False) DMAC Interrupt 0
int1outputF (False) DMAC Interrupt 1
int2outputF (False) DMAC Interrupt 2
int3outputF (False) DMAC Interrupt 3
int4outputF (False) DMAC Interrupt 4
int5outputF (False) DMAC Interrupt 5
int6outputF (False) DMAC Interrupt 6
int7outputF (False) DMAC Interrupt 7
intaoutputF (False)Interrupt DMAC Transfer Abort



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bportS

Table 1: Bus Slave Port: bportS

NameSize (bytes)Must Be ConnectedDescription
bportS0x1000T (True)

Table 2: Bus Slave Port: bportS Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
abS_DSR0x032DMA Manager Status
abS_DPC0x432DMA Program Counter
abS_INTEN0x2032DMASEV Instruction Response Control
abS_INT_EVENT_RIS0x2432Event Interrupt Raw Status
abS_INTMIS0x2832Interrupt Status
abS_INTCLR0x2c32Interrupt Clear
abS_FSRD0x3032Fault Status DMA Manager
abS_FSRC0x3432Fault Status DMA Channel
abS_FTRD0x3832Fault Type DMA Manager
abS_FTR00x4032Default Type DMA Channel 0
abS_FTR10x4432Default Type DMA Channel 1
abS_FTR20x4832Default Type DMA Channel 2
abS_FTR30x4c32Default Type DMA Channel 3
abS_FTR40x5032Default Type DMA Channel 4
abS_FTR50x5432Default Type DMA Channel 5
abS_FTR60x5832Default Type DMA Channel 6
abS_FTR70x5c32Default Type DMA Channel 7
abS_CSR00x10032Channel Status DMA Channel 0
abS_CPC00x10432Channel PC for DMA Channel 0
abS_CSR10x10832Channel Status DMA Channel 1
abS_CPC10x10c32Channel PC for DMA Channel 1
abS_CSR20x11032Channel Status DMA Channel 2
abS_CPC20x11432Channel PC for DMA Channel 2
abS_CSR30x11832Channel Status DMA Channel 3
abS_CPC30x11c32Channel PC for DMA Channel 3
abS_CSR40x12032Channel Status DMA Channel 4
abS_CPC40x12432Channel PC for DMA Channel 4
abS_CSR50x12832Channel Status DMA Channel 5
abS_CPC50x12c32Channel PC for DMA Channel 5
abS_CSR60x13032Channel Status DMA Channel 6
abS_CPC60x13432Channel PC for DMA Channel 6
abS_CSR70x13832Channel Status DMA Channel 7
abS_CPC70x13c32Channel PC for DMA Channel 7
abS_SAR00x40032Source Address DMA Channel 0
abS_DAR00x40432Destination Addr DMA Channel 0
abS_CCR00x40832Channel Control DMA Channel 0 (dmac0_ns: 0x00000000 dmac0_s: 0x00800200)
abS_LC0_00x40c32Loop Counter 0 DMA Channel 0
abS_LC1_00x41032Loop Counter 1 DMA Channel 0
abS_SAR10x42032Source address DMA Channel 1
abS_DAR10x42432Destination Addr DMA Channel 1
abS_CCR10x42832Channel Control DMA Channel 1 (dmac0_ns: 0x00000000 dmac0_s: 0x00800200 )
abS_LC0_10x42c32Loop Counter 0 DMA Channel 1
abS_LC1_10x43032Loop Counter 1 DMA Channel 1
abS_SAR20x44032Source Address DMA Channel 2
abS_DAR20x44432Destination Addr DMA Channel 2
abS_CCR20x44832Channel Control DMA Channel 2 (dmac0_ns: 0x00000000 dmac0_s: 0x00800200 )
abS_LC0_20x44c32Loop Counter 0 DMA Channel 2
abS_LC1_20x45032Loop Counter 1 DMA Channel 2
abS_SAR30x46032Source Address DMA Channel 3
abS_DAR30x46432Destination Addr DMA Channel 3
abS_CCR30x46832Channel Control DMA Channel 3 (dmac0_ns: 0x00000000 dmac0_s: 0x00800200)
abS_LC0_30x46c32Loop Counter 0 DMA Channel 3
abS_LC1_30x47032Loop Counter 1 DMA Channel 3
abS_SAR40x48032Source Address DMA Channel 4
abS_DAR40x48432Destination Addr DMA Channel 4
abS_CCR40x48832Channel Control DMA Channel 4 (dmac0_ns: 0x00000000 dmac0_s: 0x00800200 )
abS_LC0_40x48c32Loop Counter 0 DMA Channel 4
abS_LC1_40x49032Loop Counter 1 DMA Channel 4
abS_SAR50x4a032Source Address DMA Channel 5
abS_DAR50x4a432Destination Addr DMA Channel 5
abS_CCR50x4a832Channel Control DMA Channel 5 (dmac0_ns: 0x00000000 dmac0_s: 0x00800200 )
abS_LC0_50x4ac32Loop Counter 0 DMA Channel 5
abS_LC1_50x4b032Loop Counter 1 DMA Channel 5
abS_SAR60x4c032Source Address DMA Channel 6
abS_DAR60x4c432Destination Addr DMA Channel 6
abS_CCR60x4c832Channel Control DMA Channel 6 (dmac0_ns: 0x00000000 dmac0_s: 0x00800200 )
abS_LC0_60x4cc32Loop Counter 0 DMA Channel 6
abS_LC1_60x4d032Loop Counter 1 DMA Channel 6
abS_SAR70x4e032Source Address DMA Channel 7
abS_DAR70x4e432Destination Addr DMA Channel 7
abS_CCR70x4e832Channel Control DMA Channel 7 (dmac0_ns: 0x00000000 dmac0_s: 0x00800200 )
abS_LC0_70x4ec32Loop Counter 0 DMA Channel 7
abS_LC1_70x4f032Loop Counter 1 DMA Channel 7
abS_DBGSTATUS0xd0032DMA Manager Execution Status
abS_DBGCMD0xd0432DMA Manager Instr. command
abS_DBGINST00xd0832DMA Manager Instruction Part A
abS_DBGINST10xd0c32DMA Manager Instruction Part B
abS_CR00xe0032Config. 0: Events, Peripheral Interfaces, PC, Mode (dmac0_ns: 0x00000000 dmac0_s: 0x001E3071 )
abS_CR10xe0432Config. 1: Instruction Cache (dmac0_ns: 0x00000000 dmac0_s: 0x00000074 )
abS_CR20xe0832Config. 2: DMA Mgr Boot Addr
abS_CR30xe0c32Config. 3: Security state of IRQs
abS_CR40xe1032Config 4, Security of Periph Interfaces
abS_CRD0xe1432DMA configuration (dmac0_ns: 0x00000000 dmac0_s: 0x07FF7F73 )
abS_WD0xe8032Watchdog Timer
abS_periph_id_00xfe032Peripheral Identification register 0 (dmac0_ns: 0x00000000 dmac0_s: 0x00000030 )
abS_periph_id_10xfe432Peripheral Identification register 1 (dmac0_ns: 0x00000000 dmac0_s: 0x00000013 )
abS_periph_id_20xfe832Peripheral Identification register 2 (dmac0_ns: 0x00000000 dmac0_s: 0x00000024 )
abS_periph_id_30xfec32Peripheral Identification register 3
abS_pcell_id_00xff032Component Identification register 0 (dmac0_ns: 0x00000000 dmac0_s: 0x0000000D)
abS_pcell_id_10xff432Component Identification register 1 (dmac0_ns: 0x00000000 dmac0_s: 0x000000F0)
abS_pcell_id_20xff832Component Identification register 2 (dmac0_ns: 0x00000000 dmac0_s: 0x00000005)
abS_pcell_id_30xffc32Component Identification register 3 (dmac0_ns: 0x00000000 dmac0_s: 0x000000B1)

Bus Slave Port: bportNS

Table 3: Bus Slave Port: bportNS

NameSize (bytes)Must Be ConnectedDescription
bportNS0x1000T (True)

Table 4: Bus Slave Port: bportNS Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
abNS_DSR0x032DMA Manager Status
abNS_DPC0x432DMA Program Counter
abNS_INTEN0x2032DMASEV Instruction Response Control
abNS_INT_EVENT_RIS0x2432Event Interrupt Raw Status
abNS_INTMIS0x2832Interrupt Status
abNS_INTCLR0x2c32Interrupt Clear
abNS_FSRD0x3032Fault Status DMA Manager
abNS_FSRC0x3432Fault Status DMA Channel
abNS_FTRD0x3832Fault Type DMA Manager
abNS_FTR00x4032Default Type DMA Channel 0
abNS_FTR10x4432Default Type DMA Channel 1
abNS_FTR20x4832Default Type DMA Channel 2
abNS_FTR30x4c32Default Type DMA Channel 3
abNS_FTR40x5032Default Type DMA Channel 4
abNS_FTR50x5432Default Type DMA Channel 5
abNS_FTR60x5832Default Type DMA Channel 6
abNS_FTR70x5c32Default Type DMA Channel 7
abNS_CSR00x10032Channel Status DMA Channel 0
abNS_CPC00x10432Channel PC for DMA Channel 0
abNS_CSR10x10832Channel Status DMA Channel 1
abNS_CPC10x10c32Channel PC for DMA Channel 1
abNS_CSR20x11032Channel Status DMA Channel 2
abNS_CPC20x11432Channel PC for DMA Channel 2
abNS_CSR30x11832Channel Status DMA Channel 3
abNS_CPC30x11c32Channel PC for DMA Channel 3
abNS_CSR40x12032Channel Status DMA Channel 4
abNS_CPC40x12432Channel PC for DMA Channel 4
abNS_CSR50x12832Channel Status DMA Channel 5
abNS_CPC50x12c32Channel PC for DMA Channel 5
abNS_CSR60x13032Channel Status DMA Channel 6
abNS_CPC60x13432Channel PC for DMA Channel 6
abNS_CSR70x13832Channel Status DMA Channel 7
abNS_CPC70x13c32Channel PC for DMA Channel 7
abNS_SAR00x40032Source Address DMA Channel 0
abNS_DAR00x40432Destination Addr DMA Channel 0
abNS_CCR00x40832Channel Control DMA Channel 0 (dmac0_ns: 0x00000000 dmac0_s: 0x00800200)
abNS_LC0_00x40c32Loop Counter 0 DMA Channel 0
abNS_LC1_00x41032Loop Counter 1 DMA Channel 0
abNS_SAR10x42032Source address DMA Channel 1
abNS_DAR10x42432Destination Addr DMA Channel 1
abNS_CCR10x42832Channel Control DMA Channel 1 (dmac0_ns: 0x00000000 dmac0_s: 0x00800200 )
abNS_LC0_10x42c32Loop Counter 0 DMA Channel 1
abNS_LC1_10x43032Loop Counter 1 DMA Channel 1
abNS_SAR20x44032Source Address DMA Channel 2
abNS_DAR20x44432Destination Addr DMA Channel 2
abNS_CCR20x44832Channel Control DMA Channel 2 (dmac0_ns: 0x00000000 dmac0_s: 0x00800200 )
abNS_LC0_20x44c32Loop Counter 0 DMA Channel 2
abNS_LC1_20x45032Loop Counter 1 DMA Channel 2
abNS_SAR30x46032Source Address DMA Channel 3
abNS_DAR30x46432Destination Addr DMA Channel 3
abNS_CCR30x46832Channel Control DMA Channel 3 (dmac0_ns: 0x00000000 dmac0_s: 0x00800200)
abNS_LC0_30x46c32Loop Counter 0 DMA Channel 3
abNS_LC1_30x47032Loop Counter 1 DMA Channel 3
abNS_SAR40x48032Source Address DMA Channel 4
abNS_DAR40x48432Destination Addr DMA Channel 4
abNS_CCR40x48832Channel Control DMA Channel 4 (dmac0_ns: 0x00000000 dmac0_s: 0x00800200 )
abNS_LC0_40x48c32Loop Counter 0 DMA Channel 4
abNS_LC1_40x49032Loop Counter 1 DMA Channel 4
abNS_SAR50x4a032Source Address DMA Channel 5
abNS_DAR50x4a432Destination Addr DMA Channel 5
abNS_CCR50x4a832Channel Control DMA Channel 5 (dmac0_ns: 0x00000000 dmac0_s: 0x00800200 )
abNS_LC0_50x4ac32Loop Counter 0 DMA Channel 5
abNS_LC1_50x4b032Loop Counter 1 DMA Channel 5
abNS_SAR60x4c032Source Address DMA Channel 6
abNS_DAR60x4c432Destination Addr DMA Channel 6
abNS_CCR60x4c832Channel Control DMA Channel 6 (dmac0_ns: 0x00000000 dmac0_s: 0x00800200 )
abNS_LC0_60x4cc32Loop Counter 0 DMA Channel 6
abNS_LC1_60x4d032Loop Counter 1 DMA Channel 6
abNS_SAR70x4e032Source Address DMA Channel 7
abNS_DAR70x4e432Destination Addr DMA Channel 7
abNS_CCR70x4e832Channel Control DMA Channel 7 (dmac0_ns: 0x00000000 dmac0_s: 0x00800200 )
abNS_LC0_70x4ec32Loop Counter 0 DMA Channel 7
abNS_LC1_70x4f032Loop Counter 1 DMA Channel 7
abNS_DBGSTATUS0xd0032DMA Manager Execution Status
abNS_DBGCMD0xd0432DMA Manager Instr. command
abNS_DBGINST00xd0832DMA Manager Instruction Part A
abNS_DBGINST10xd0c32DMA Manager Instruction Part B
abNS_CR00xe0032Config. 0: Events, Peripheral Interfaces, PC, Mode (dmac0_ns: 0x00000000 dmac0_s: 0x001E3071 )
abNS_CR10xe0432Config. 1: Instruction Cache (dmac0_ns: 0x00000000 dmac0_s: 0x00000074 )
abNS_CR20xe0832Config. 2: DMA Mgr Boot Addr
abNS_CR30xe0c32Config. 3: Security state of IRQs
abNS_CR40xe1032Config 4, Security of Periph Interfaces
abNS_CRD0xe1432DMA configuration (dmac0_ns: 0x00000000 dmac0_s: 0x07FF7F73 )
abNS_WD0xe8032Watchdog Timer
abNS_periph_id_00xfe032Peripheral Identification register 0 (dmac0_ns: 0x00000000 dmac0_s: 0x00000030 )
abNS_periph_id_10xfe432Peripheral Identification register 1 (dmac0_ns: 0x00000000 dmac0_s: 0x00000013 )
abNS_periph_id_20xfe832Peripheral Identification register 2 (dmac0_ns: 0x00000000 dmac0_s: 0x00000024 )
abNS_periph_id_30xfec32Peripheral Identification register 3
abNS_pcell_id_00xff032Component Identification register 0 (dmac0_ns: 0x00000000 dmac0_s: 0x0000000D)
abNS_pcell_id_10xff432Component Identification register 1 (dmac0_ns: 0x00000000 dmac0_s: 0x000000F0)
abNS_pcell_id_20xff832Component Identification register 2 (dmac0_ns: 0x00000000 dmac0_s: 0x00000005)
abNS_pcell_id_30xffc32Component Identification register 3 (dmac0_ns: 0x00000000 dmac0_s: 0x000000B1)



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 5: Publicly available platforms using peripheral 'zynq_7000-dmac'

Platform NameVendor
Zynq_PSxilinx.ovpworld.org



XilinxPeripherals
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