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XilinxZynq_7000Iic



OVP Peripheral Model: XilinxZynq_7000Iic



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

Zynq 7000 I2C Registers. This model also includes the behaviour for PCA9548 I2C Bus Switch

Licensing

Open Source Apache 2.0

Limitations

This model implements the full set of registers and behaviour to read and write the I2C address space.

Reference

Zynq-7000 TRM (https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf).

Evaluation Board ZC706 (ug954-zc706-eval-board-xc7z045-ap-soc.pdf)

Evaluation Board ZC702 (ug850-zc702-eval-board.pdf)

Location

The zynq_7000-iic peripheral model is located in an Imperas/OVP installation at the VLNV: xilinx.ovpworld.org / peripheral / zynq_7000-iic / 1.0.



Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

NameTypeDescription
PCLKuns32The Peripheral clock frequency in MHz (default 133 MHz)



Net Ports

This model has the following net ports:

Table 1: Net Ports

NameTypeMust Be ConnectedDescription
intOutoutputF (False)



Bus Master Ports

This model has the following bus master ports:

Bus Master Port: I2C_Master

Table 2: I2C_Master

NameAddress Width (bits)Description
I2C_Master10



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: I2C_Slave

Table 3: Bus Slave Port: I2C_Slave

NameSize (bytes)Must Be ConnectedDescription
I2C_Slave0x4F (False)


No address blocks have been defined for this slave port.

Bus Slave Port: bport1

Table 4: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x1000T (True)

Table 5: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_Control0x032Control register
ab_I2CAddress0x832I2C Address register
ab_I2CData0xc32I2C Data register
ab_TransferSize0x1432Transfer Size register
ab_SlaveMonPause0x1832Slave Monitor Pause register
ab_TimeOut0x1c32Time Out register
ab_InterruptMask0x2032Interrupt Mask register
ab_InterruptEnable0x2432Interrupt Enable register
ab_InterruptDisable0x2832Interrupt Disable register



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 6: Publicly available platforms using peripheral 'zynq_7000-iic'

Platform NameVendor
Zynq_PSxilinx.ovpworld.org



XilinxPeripherals
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