OVP Peripheral Model: XilinxZynq_7000Ocm

Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.


Zynq 7000 Platform On Chip Memory Controller Registers (OCM)


Open Source Apache 2.0


This model implements the full set of registers. There is no behavior included.


Zynq-7000 TRM (


The zynq_7000-ocm peripheral model is located in an Imperas/OVP installation at the VLNV: / peripheral / zynq_7000-ocm / 1.0.

Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table : Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x1000T (True)

Table 1: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_OCM_PARITY_CTRL0x032Control fields for RAM parity operation
ab_OCM_PARITY_ERRADDRESS0x432Stores the first parity error access address. This register is sticky and will retain its value unless explicitly cleared (written with 1's) with an APB write access. The physical RAM address is logged.
ab_OCM_IRQ_STS0x832Status of OCM Interrupt
ab_OCM_CONTROL0xc32Control fields for OCM

Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 2: Publicly available platforms using peripheral 'zynq_7000-ocm'

Platform NameVendor

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