OVP Peripheral Model: XilinxZynq_7000Qspi

Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.


Zynq 7000 Quad-SPI Registers and incorporates Flash Memory (Spansion and Micron) for Zync zc702/zc706 boards


Open Source Apache 2.0


This model implements the full set of registers but not all flash memory accesses are supported.

The model is tested using Xilinx Example Project for R/W a QPSI memory on ZC702 platform using Polled and Interrupt driven Transfers.

The AXI mode of operation is not tested. There is no write protection implemented for memory access when in AXI mode.


Zynq-7000 TRM (


The zynq_7000-qspi peripheral model is located in an Imperas/OVP installation at the VLNV: / peripheral / zynq_7000-qspi / 1.0.

Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

imagestringSpecify a file to initialize flash memory. String of form <file>[@<offset>]
imageoutstringSpecify a file to write the flash memory at the end of simulation. String of form <file>[@<offset>][:<size>]
flashstringDescription Specify the type of flash memory, 'spansion' or 'micron' (default) Limitations The Spansion Flash memory device is not tested. The Micron flash memory device is tested using the Xilinx example program.

Net Ports

This model has the following net ports:

Table 1: Net Ports

NameTypeMust Be ConnectedDescription
interruptoutputF (False)Interrupt signal

Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bpAXI

Table 2: Bus Slave Port: bpAXI

NameSize (bytes)Must Be ConnectedDescription
bpAXI0x2000000T (True)

No address blocks have been defined for this slave port.

Bus Slave Port: bpAPB

Table 3: Bus Slave Port: bpAPB

NameSize (bytes)Must Be ConnectedDescription
bpAPB0x1000T (True)

Table 4: Bus Slave Port: bpAPB Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_Config_reg0x032QSPI configuration register
ab_Intr_status_REG0x432QSPI interrupt status register
ab_Intrpt_en_REG0x832Interrupt Enable register.
ab_Intrpt_dis_REG0xc32Interrupt disable register.
ab_Intrpt_mask_REG0x1032Interrupt mask register
ab_En_REG0x1432SPI_Enable Register
ab_Delay_REG0x1832Delay Register
ab_TXD00x1c32Transmit Data Register. Keyhole addresses for the Transmit data FIFO. See also TXD1-3.
ab_Rx_data_REG0x2032Receive Data Register
ab_Slave_Idle_count_REG0x2432Slave Idle Count Register
ab_TX_thres_REG0x2832TX_FIFO Threshold Register
ab_RX_thres_REG0x2c32RX FIFO Threshold Register
ab_GPIO0x3032General Purpose Inputs and Outputs Register for the Quad-SPI Controller core
ab_LPBK_DLY_ADJ0x3832Loopback Master Clock Delay Adjustment Register
ab_TXD10x8032Transmit Data Register. Keyhole addresses for the Transmit data FIFO.
ab_TXD20x8432Transmit Data Register. Keyhole addresses for the Transmit data FIFO.
ab_TXD30x8832Transmit Data Register. Keyhole addresses for the Transmit data FIFO.
ab_LQSPI_CFG0xa032Configuration Register specifically for the Linear Quad-SPI Controller
ab_LQSPI_STS0xa432Status Register specifically for the Linear Quad-SPI Controller
ab_MOD_ID0xfc32Module Identification register

Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 5: Publicly available platforms using peripheral 'zynq_7000-qspi'

Platform NameVendor

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