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XilinxZynq_7000Slcr



OVP Peripheral Model: XilinxZynq_7000Slcr



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

Zynq 7000 Platform System Level Control Registers (SLCR)

Licensing

Open Source Apache 2.0

Limitations

This model implements the full set of registers. Only behavior required for processor reset control is included.

Reference

Zynq-7000 TRM (https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf)

Location

The zynq_7000-slcr peripheral model is located in an Imperas/OVP installation at the VLNV: xilinx.ovpworld.org / peripheral / zynq_7000-slcr / 1.0.



Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

NameTypeDescription
lockcodeuns32
unlockcodeuns32
deviceiduns32
devicerevuns32
psclockuns32Define the master clock (PS_CLK) frequency in MHz (default 33)
armmipsuns32Define ARM CPU MIPS Rate in MIPS (default 500)
bootmodeuns32Define BOOT_MODE value (default 0x04)
clockcontroldisableboolDisable change to ARM processor operating frequency when ARM PLL or clock control registers are modified.



Net Ports

This model has the following net ports:

Table 1: Net Ports

NameTypeMust Be ConnectedDescription
A9_RST0outputF (False)
A9_RST1outputF (False)
ARM1DerationoutputF (False)
ARM0DerationoutputF (False)



Bus Master Ports

This model has the following bus master ports:

Bus Master Port: mpOCM

Table 2: mpOCM

NameAddress Width (bits)Description
mpOCM32

Bus Master Port: mpDDR

Table 3: mpDDR

NameAddress Width (bits)Description
mpDDR32



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 4: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10xc00T (True)

Table 5: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_SCL0x032Secure Configuration Lock
ab_SLCR_LOCK0x432SLCR Write Protection Lock
ab_SLCR_UNLOCK0x832SLCR Write Protection Unlock
ab_SLCR_LOCKSTA0xc32SLCR Write Protection Status
ab_ARM_PLL_CTRL0x10032ARM PLL Control
ab_DDR_PLL_CTRL0x10432DDR PLL Control
ab_IO_PLL_CTRL0x10832IO PLL Control
ab_PLL_STATUS0x10c32PLL Status
ab_ARM_PLL_CFG0x11032ARM PLL Configuration
ab_DDR_PLL_CFG0x11432DDR PLL Configuration
ab_IO_PLL_CFG0x11832IO PLL Configuration
ab_ARM_CLK_CTRL0x12032CPU Clock Control
ab_DDR_CLK_CTRL0x12432DDR Clock Control
ab_DCI_CLK_CTRL0x12832DCI clock control
ab_APER_CLK_CTRL0x12c32AMBA Peripheral Clock Control
ab_USB0_CLK_CTRL0x13032USB 0 ULPI Clock Control
ab_USB1_CLK_CTRL0x13432USB 1 ULPI Clock Control
ab_GEM0_RCLK_CTRL0x13832GigE 0 Rx Clock and Rx Signals Select
ab_GEM1_RCLK_CTRL0x13c32GigE 1 Rx Clock and Rx Signals Select
ab_GEM0_CLK_CTRL0x14032GigE 0 Ref Clock Control
ab_GEM1_CLK_CTRL0x14432GigE 1 Ref Clock Control
ab_SMC_CLK_CTRL0x14832SMC Ref Clock Control
ab_LQSPI_CLK_CTRL0x14c32Quad SPI Ref Clock Control
ab_SDIO_CLK_CTRL0x15032SDIO Ref Clock Control
ab_UART_CLK_CTRL0x15432UART Ref Clock Control
ab_SPI_CLK_CTRL0x15832SPI Ref Clock Control
ab_CAN_CLK_CTRL0x15c32CAN Ref Clock Control
ab_CAN_MIOCLK_CTRL0x16032CAN MIO Clock Control
ab_DBG_CLK_CTRL0x16432SoC Debug Clock Control
ab_PCAP_CLK_CTRL0x16832PCAP Clock Control
ab_TOPSW_CLK_CTRL0x16c32Central Interconnect Clock Control
ab_FPGA0_CLK_CTRL0x17032PL Clock 0 Output control
ab_FPGA0_THR_CTRL0x17432PL Clock 0 Throttle control
ab_FPGA0_THR_CNT0x17832PL Clock 0 Throttle Count control
ab_FPGA0_THR_STA0x17c32PL Clock 0 Throttle Status read
ab_FPGA1_CLK_CTRL0x18032PL Clock 1 Output control
ab_FPGA1_THR_CTRL0x18432PL Clock 1 Throttle control
ab_FPGA1_THR_CNT0x18832PL Clock 1 Throttle Count
ab_FPGA1_THR_STA0x18c32PL Clock 1 Throttle Status control
ab_FPGA2_CLK_CTRL0x19032PL Clock 2 output control
ab_FPGA2_THR_CTRL0x19432PL Clock 2 Throttle Control
ab_FPGA2_THR_CNT0x19832PL Clock 2 Throttle Count
ab_FPGA2_THR_STA0x19c32PL Clock 2 Throttle Status
ab_FPGA3_CLK_CTRL0x1a032PL Clock 3 output control
ab_FPGA3_THR_CTRL0x1a432PL Clock 3 Throttle Control
ab_FPGA3_THR_CNT0x1a832PL Clock 3 Throttle Count
ab_FPGA3_THR_STA0x1ac32PL Clock 3 Throttle Status
ab_CLK_621_TRUE0x1c432CPU Clock Ratio Mode select
ab_PSS_RST_CTRL0x20032PS Software Reset Control
ab_DDR_RST_CTRL0x20432DDR Software Reset Control
ab_TOPSW_RST_CTRL0x20832Central Interconnect Reset Control
ab_DMAC_RST_CTRL0x20c32DMAC Software Reset Control
ab_USB_RST_CTRL0x21032USB Software Reset Control
ab_GEM_RST_CTRL0x21432Gigabit Ethernet SW Reset Control
ab_SDIO_RST_CTRL0x21832SDIO Software Reset Control
ab_SPI_RST_CTRL0x21c32SPI Software Reset Control
ab_CAN_RST_CTRL0x22032CAN Software Reset Control
ab_I2C_RST_CTRL0x22432I2C Software Reset Control
ab_UART_RST_CTRL0x22832UART Software Reset Control
ab_GPIO_RST_CTRL0x22c32GPIO Software Reset Control
ab_LQSPI_RST_CTRL0x23032Quad SPI Software Reset Control
ab_SMC_RST_CTRL0x23432SMC Software Reset Control
ab_OCM_RST_CTRL0x23832OCM Software Reset Control
ab_FPGA_RST_CTRL0x24032FPGA Software Reset Control
ab_A9_CPU_RST_CTRL0x24432CPU Reset and Clock control
ab_RS_AWDT_CTRL0x24c32Watchdog Timer Reset Control
ab_REBOOT_STATUS0x25832Reboot Status, persistent
ab_BOOT_MODE0x25c32Boot Mode Strapping Pins
ab_APU_CTRL0x30032APU Control
ab_WDT_CLK_SEL0x30432SWDT clock source select
ab_TZ_OCM_RAM00x40032OCM RAM TrustZone Config 0
ab_TZ_OCM_RAM10x40432OCM RAM TrustZone Config 1
ab_TZ_OCM0x40832OCM ROM TrustZone Config
ab_TZ_DDR_RAM0x43032DDR RAM TrustZone Config
ab_TZ_DMA_NS0x44032DMAC TrustZone Config
ab_TZ_DMA_IRQ_NS0x44432DMAC TrustZone Config for Interrupts
ab_TZ_DMA_PERIPH_NS0x44832DMAC TrustZone Config for Peripherals
ab_TZ_GEM0x45032Ethernet TrustZone Config
ab_TZ_SDIO0x45432SDIO TrustZone Config
ab_TZ_USB0x45832USB TrustZone Config
ab_TZ_FPGA_M0x48432FPGA master ports TrustZone Disable
ab_TZ_FPGA_AFI0x48832FPGA AFI AXI ports TrustZone Disable
ab_PSS_IDCODE0x53032PS IDCODE (REVISION=1 FAMILY=0x1b SUBFAMILY=0x9 DEVICE=0x11 (7z045) MANUFACTURE_ID=0x49
ab_DDR_URGENT0x60032DDR Urgent Control
ab_DDR_CAL_START0x60c32DDR Calibration Start Triggers
ab_DDR_REF_START0x61432DDR Refresh Start Triggers
ab_DDR_CMD_STA0x61832DDR Command Store Status
ab_DDR_URGENT_SEL0x61c32DDR Urgent Select
ab_DDR_DFI_STATUS0x62032DDR DFI status
ab_MIO_PIN_000x70032MIO Pin 0 Control
ab_MIO_PIN_010x70432MIO Pin 1 Control
ab_MIO_PIN_020x70832MIO Pin 2 Control
ab_MIO_PIN_030x70c32MIO Pin 3 Control
ab_MIO_PIN_040x71032MIO Pin 4 Control
ab_MIO_PIN_050x71432MIO Pin 5 Control
ab_MIO_PIN_060x71832MIO Pin 6 Control
ab_MIO_PIN_070x71c32MIO Pin 7 Control
ab_MIO_PIN_080x72032MIO Pin 8 Control
ab_MIO_PIN_090x72432MIO Pin 9 Control
ab_MIO_PIN_100x72832MIO Pin 10 Control
ab_MIO_PIN_110x72c32MIO Pin 11 Control
ab_MIO_PIN_120x73032MIO Pin 12 Control
ab_MIO_PIN_130x73432MIO Pin 13 Control
ab_MIO_PIN_140x73832MIO Pin 14 Control
ab_MIO_PIN_150x73c32MIO Pin 15 Control
ab_MIO_PIN_160x74032MIO Pin 16 Control
ab_MIO_PIN_170x74432MIO Pin 17 Control
ab_MIO_PIN_180x74832MIO Pin 18 Control
ab_MIO_PIN_190x74c32MIO Pin 19 Control
ab_MIO_PIN_200x75032MIO Pin 20 Control
ab_MIO_PIN_210x75432MIO Pin 21 Control
ab_MIO_PIN_220x75832MIO Pin 22 Control
ab_MIO_PIN_230x75c32MIO Pin 23 Control
ab_MIO_PIN_240x76032MIO Pin 24 Control
ab_MIO_PIN_250x76432MIO Pin 25 Control
ab_MIO_PIN_260x76832MIO Pin 26 Control
ab_MIO_PIN_270x76c32MIO Pin 27 Control
ab_MIO_PIN_280x77032MIO Pin 28 Control
ab_MIO_PIN_290x77432MIO Pin 29 Control
ab_MIO_PIN_300x77832MIO Pin 30 Control
ab_MIO_PIN_310x77c32MIO Pin 31 Control
ab_MIO_PIN_320x78032MIO Pin 32 Control
ab_MIO_PIN_330x78432MIO Pin 33 Control
ab_MIO_PIN_340x78832MIO Pin 34 Control
ab_MIO_PIN_350x78c32MIO Pin 35 Control
ab_MIO_PIN_360x79032MIO Pin 36 Control
ab_MIO_PIN_370x79432MIO Pin 37 Control
ab_MIO_PIN_380x79832MIO Pin 38 Control
ab_MIO_PIN_390x79c32MIO Pin 39 Control
ab_MIO_PIN_400x7a032MIO Pin 40 Control
ab_MIO_PIN_410x7a432MIO Pin 41 Control
ab_MIO_PIN_420x7a832MIO Pin 42 Control
ab_MIO_PIN_430x7ac32MIO Pin 43 Control
ab_MIO_PIN_440x7b032MIO Pin 44 Control
ab_MIO_PIN_450x7b432MIO Pin 45 Control
ab_MIO_PIN_460x7b832MIO Pin 46 Control
ab_MIO_PIN_470x7bc32MIO Pin 47 Control
ab_MIO_PIN_480x7c032MIO Pin 48 Control
ab_MIO_PIN_490x7c432MIO Pin 49 Control
ab_MIO_PIN_500x7c832MIO Pin 50 Control
ab_MIO_PIN_510x7cc32MIO Pin 51 Control
ab_MIO_PIN_520x7d032MIO Pin 52 Control
ab_MIO_PIN_530x7d432MIO Pin 53 Control
ab_MIO_LOOPBACK0x80432Loopback function within MIO
ab_MIO_MST_TRI00x80c32MIO pin Tri-state Enables, 31:0
ab_MIO_MST_TRI10x81032MIO pin Tri-state Enables, 53:32
ab_SD0_WP_CD_SEL0x83032SDIO 0 WP CD select
ab_SD1_WP_CD_SEL0x83432SDIO 1 WP CD select
ab_LVL_SHFTR_EN0x90032Level Shifters Enable
ab_OCM_CFG0x91032OCM Address Mapping (user mode reset config)
ab_Reserved0xa1c32Reserved
ab_GPIOB_CTRL0xb0032PS IO Buffer Control
ab_GPIOB_CFG_CMOS180xb0432MIO GPIOB CMOS 1.8V config
ab_GPIOB_CFG_CMOS250xb0832MIO GPIOB CMOS 2.5V config
ab_GPIOB_CFG_CMOS330xb0c32MIO GPIOB CMOS 3.3V config
ab_GPIOB_CFG_HSTL0xb1432MIO GPIOB HSTL config
ab_GPIOB_DRVR_BIAS_CTRL0xb1832MIO GPIOB Driver Bias Control
ab_DDRIOB_ADDR00xb4032DDR IOB Config for A[14:0], CKE and DRST_B
ab_DDRIOB_ADDR10xb4432DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B
ab_DDRIOB_DATA00xb4832DDR IOB Config for Data 15:0
ab_DDRIOB_DATA10xb4c32DDR IOB Config for Data 31:16
ab_DDRIOB_DIFF00xb5032DDR IOB Config for DQS 1:0
ab_DDRIOB_DIFF10xb5432DDR IOB Config for DQS 3:2
ab_DDRIOB_CLOCK0xb5832DDR IOB Config for Clock Output
ab_DDRIOB_DRIVE_SLEW_ADDR0xb5c32Drive and Slew controls for Address and Command pins of the DDR Interface
ab_DDRIOB_DRIVE_SLEW_DATA0xb6032Drive and Slew controls for DQ pins of the DDR Interface
ab_DDRIOB_DRIVE_SLEW_DIFF0xb6432Drive and Slew controls for DQS pins of the DDR Interface
ab_DDRIOB_DRIVE_SLEW_CLOCK0xb6832Drive and Slew controls for Clock pins of the DDR Interface
ab_DDRIOB_DDR_CTRL0xb6c32DDR IOB Buffer Control
ab_DDRIOB_DCI_CTRL0xb7032DDR IOB DCI Config
ab_DDRIOB_DCI_STATUS0xb7432DDR IO Buffer DCI Status

Bus Slave Port: spOCMDDR

Table 6: Bus Slave Port: spOCMDDR

NameSize (bytes)Must Be ConnectedDescription
spOCMDDR0x1T (True)


No address blocks have been defined for this slave port.



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 7: Publicly available platforms using peripheral 'zynq_7000-slcr'

Platform NameVendor
Zynq_PSxilinx.ovpworld.org



XilinxPeripherals
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