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XilinxZynq_7000Ttc



OVP Peripheral Model: XilinxZynq_7000Ttc



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

Zynq 7000 Triple Timer Counter Registers

Licensing

Open Source Apache 2.0

Limitations

This model implements the full set of registers and basic behavior. It is not yet completed.

Reference

Zynq-7000 TRM (https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf)

Location

The zynq_7000-ttc peripheral model is located in an Imperas/OVP installation at the VLNV: xilinx.ovpworld.org / peripheral / zynq_7000-ttc / 1.0.



Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

NameTypeDescription
clk1uns32Timer 1 Clock Rate MHz (default 33MHz)
clk2uns32Timer 2 Clock Rate MHz (default 33MHz)
clk3uns32Timer 3 Clock Rate MHz (default 33MHz)
endianstringSpecify the endian of the processor interface (default little endian)



Net Ports

This model has the following net ports:

Table 1: Net Ports

NameTypeMust Be ConnectedDescription
int1outputF (False)Interrupt Timer 1
int2outputF (False)Interrupt Timer 2
int3outputF (False)Interrupt Timer 3



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 2: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x1000T (True)

Table 3: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_Clock_Control_10x032Clock Control register
ab_Clock_Control_20x432Clock Control register
ab_Clock_Control_30x832Clock Control register
ab_Counter_Control_10xc32Operational mode and reset
ab_Counter_Control_20x1032Operational mode and reset
ab_Counter_Control_30x1432Operational mode and reset
ab_Counter_Value_10x1832Current counter value
ab_Counter_Value_20x1c32Current counter value
ab_Counter_Value_30x2032Current counter value
ab_Interval_Counter_10x2432Interval value
ab_Interval_Counter_20x2832Interval value
ab_Interval_Counter_30x2c32Interval value
ab_Match_1_Counter_10x3032Match value
ab_Match_1_Counter_20x3432Match value
ab_Match_1_Counter_30x3832Match value
ab_Match_2_Counter_10x3c32Match value
ab_Match_2_Counter_20x4032Match value
ab_Match_2_Counter_30x4432Match value
ab_Match_3_Counter_10x4832Match value
ab_Match_3_Counter_20x4c32Match value
ab_Match_3_Counter_30x5032Match value
ab_Interrupt_Register_10x5432Counter 1 Interval, Match, Overflow and Event interrupts
ab_Interrupt_Register_20x5832Counter 2 Interval, Match, Overflow and Event interrupts
ab_Interrupt_Register_30x5c32Counter 3 Interval, Match, Overflow and Event interrupts
ab_Interrupt_Enable_10x6032ANDed with corresponding Interrupt Register
ab_Interrupt_Enable_20x6432ANDed with corresponding Interrupt Register
ab_Interrupt_Enable_30x6832ANDed with corresponding Interrupt Register
ab_Event_Control_Timer_10x6c32Enable, pulse and overflow
ab_Event_Control_Timer_20x7032Enable, pulse and overflow
ab_Event_Control_Timer_30x7432Enable, pulse and overflow
ab_Event_Register_10x7832pclk cycle count for event
ab_Event_Register_20x7c32pclk cycle count for event
ab_Event_Register_30x8032pclk cycle count for event



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 4: Publicly available platforms using peripheral 'zynq_7000-ttc'

Platform NameVendor
Zynq_PSxilinx.ovpworld.org



XilinxPeripherals
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