LIBRARY  |  COMPANIES |   PLATFORMS |   PROCESSORS |   PERIPHERALS
ZynQ



OVP Virtual Platform: Zynq

This page provides detailed information about the OVP Virtual Platform Model of the xilinx.ovpworld.org Zynq platform.

Licensing

Open Source Apache 2.0

Description

This module implements the Zynq 7000

Limitations

This module provides the instantiation of a Processing Sub-system (Zynq_PS) module and a Programmable Logic (Zynq_PL) module.

Reference

Zynq-7000 AP SoC Technical Reference Manual UG585 (v1.10) February 23, 2015 (https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf)

Location

The Zynq virtual platform is located in an Imperas/OVP installation at the VLNV: xilinx.ovpworld.org / module / Zynq / 1.0.

Platform Summary

Table : Components in platform

TypeInstanceVendorComponent
ModuleZynq_PSxilinx.ovpworld.orgZynq_PS
ModuleZynq_PLplmodulevendorplmoduletype
Busi2cBus(builtin)address width:16
BusicBus(builtin)address width:32

Platform Simulation Attributes

Table 1: Platform Simulation Attributes

AttributeValueDescription
stoponctrlcstoponctrlcStop on control-C



External Ports for Module Zynq

Table 2: External Ports

Port TypePort NameInternal Connection
busportextPortI2Ci2cBus
netportextPortXADCMuxxadcmux
netportgpio_bank0_outPgpio_bank0_out
netportgpio_bank1_outPgpio_bank1_out
netportgpio_bank0_inPgpio_bank0_in
netportgpio_bank1_inPgpio_bank1_in



Sub-Module [xilinx.ovpworld.org/module/Zynq_PS/1.0] instance: Zynq_PS

Table 3: Sub-Module Instance 'Zynq_PS' Connections

Port TypePort NameConnection
busportextPortI2Ci2cBus
netportextPortXADCMuxxadcmux
busportextPorticBus
netportgpio_bank0_outPgpio_bank0_out
netportgpio_bank0_inPgpio_bank0_in
netportgpio_bank1_outPgpio_bank1_out
netportgpio_bank1_inPgpio_bank1_in
netportgpio_bank2_outPgpio_bank2_out
netportgpio_bank2_oen_outPgpio_bank2_oen_out
netportgpio_bank2_inPgpio_bank2_in
netportgpio_bank3_outPgpio_bank3_out
netportgpio_bank3_oen_outPgpio_bank3_oen_out
netportgpio_bank3_inPgpio_bank3_in
netportirqf2p0_inPirqf2p0
netportirqf2p1_inPirqf2p1
netportirqf2p2_inPirqf2p2
netportirqf2p3_inPirqf2p3
netportirqf2p4_inPirqf2p4
netportirqf2p5_inPirqf2p5
netportirqf2p6_inPirqf2p6
netportirqf2p7_inPirqf2p7
netportirqf2p8_inPirqf2p8
netportirqf2p9_inPirqf2p9
netportirqf2p10_inPirqf2p10
netportirqf2p11_inPirqf2p11
netportirqf2p12_inPirqf2p12
netportirqf2p13_inPirqf2p13
netportirqf2p14_inPirqf2p14
netportirqf2p15_inPirqf2p15
netportirqf2p16_inPirqf2p16
netportirqf2p17_inPirqf2p17
netportirqf2p18_inPirqf2p18
netportirqf2p19_inPirqf2p19
netportirqp2f0_outPirqp2f0
netportirqp2f1_outPirqp2f1
netportirqp2f2_outPirqp2f2
netportirqp2f3_outPirqp2f3
netportirqp2f4_outPirqp2f4
netportirqp2f5_outPirqp2f5
netportirqp2f6_outPirqp2f6
netportirqp2f7_outPirqp2f7
netportirqp2f8_outPirqp2f8
netportirqp2f9_outPirqp2f9
netportirqp2f10_outPirqp2f10
netportirqp2f11_outPirqp2f11
netportirqp2f12_outPirqp2f12
netportirqp2f13_outPirqp2f13
netportirqp2f14_outPirqp2f14
netportirqp2f15_outPirqp2f15
netportirqp2f16_outPirqp2f16
netportirqp2f17_outPirqp2f17
netportirqp2f18_outPirqp2f18
netportirqp2f19_outPirqp2f19
netportirqp2f20_outPirqp2f20
netportirqp2f21_outPirqp2f21
netportirqp2f22_outPirqp2f22
netportirqp2f23_outPirqp2f23
netportirqp2f24_outPirqp2f24
netportirqp2f25_outPirqp2f25
netportirqp2f26_outPirqp2f26
netportirqp2f27_outPirqp2f27
netportirqp2f28_outPirqp2f28



Sub-Module [plmodulevendor/module/plmoduletype/1.0] instance: Zynq_PL

Table 4: Sub-Module Instance 'Zynq_PL' Connections

Port TypePort NameConnection
busportextPorticBus
netportgpio_bank2_outPgpio_bank2_out
netportgpio_bank2_oen_outPgpio_bank2_oen_out
netportgpio_bank2_inPgpio_bank2_in
netportgpio_bank3_outPgpio_bank3_out
netportgpio_bank3_oen_outPgpio_bank3_oen_out
netportgpio_bank3_inPgpio_bank3_in
netportirqf2p0_outPirqf2p0
netportirqf2p1_outPirqf2p1
netportirqf2p2_outPirqf2p2
netportirqf2p3_outPirqf2p3
netportirqf2p4_outPirqf2p4
netportirqf2p5_outPirqf2p5
netportirqf2p6_outPirqf2p6
netportirqf2p7_outPirqf2p7
netportirqf2p8_outPirqf2p8
netportirqf2p9_outPirqf2p9
netportirqf2p10_outPirqf2p10
netportirqf2p11_outPirqf2p11
netportirqf2p12_outPirqf2p12
netportirqf2p13_outPirqf2p13
netportirqf2p14_outPirqf2p14
netportirqf2p15_outPirqf2p15
netportirqf2p16_outPirqf2p16
netportirqf2p17_outPirqf2p17
netportirqf2p18_outPirqf2p18
netportirqf2p19_outPirqf2p19
netportirqp2f0_inPirqp2f0
netportirqp2f1_inPirqp2f1
netportirqp2f2_inPirqp2f2
netportirqp2f3_inPirqp2f3
netportirqp2f4_inPirqp2f4
netportirqp2f5_inPirqp2f5
netportirqp2f6_inPirqp2f6
netportirqp2f7_inPirqp2f7
netportirqp2f8_inPirqp2f8
netportirqp2f9_inPirqp2f9
netportirqp2f10_inPirqp2f10
netportirqp2f11_inPirqp2f11
netportirqp2f12_inPirqp2f12
netportirqp2f13_inPirqp2f13
netportirqp2f14_inPirqp2f14
netportirqp2f15_inPirqp2f15
netportirqp2f16_inPirqp2f16
netportirqp2f17_inPirqp2f17
netportirqp2f18_inPirqp2f18
netportirqp2f19_inPirqp2f19
netportirqp2f20_inPirqp2f20
netportirqp2f21_inPirqp2f21
netportirqp2f22_inPirqp2f22
netportirqp2f23_inPirqp2f23
netportirqp2f24_inPirqp2f24
netportirqp2f25_inPirqp2f25
netportirqp2f26_inPirqp2f26
netportirqp2f27_inPirqp2f27
netportirqp2f28_inPirqp2f28



XilinxPlatforms
Page was generated in 0.0194 seconds