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ZynqPLNostrumNoCnode



OVP Virtual Platform: Zynq_PL_NostrumNoC_node

This page provides detailed information about the OVP Virtual Platform Model of the safepower.ovpworld.org Zynq_PL_NostrumNoC_node platform.

Licensing

Open Source Apache 2.0

Description

This module implements a NoC node used to implement an example NoC in the Xilinx Zynq Programmable Logic (PL). This PL configuration instances one Xilinx MicroBlaze processor with a local memory and a NoC interface peripheral.

Limitations

This is baremetal only.

Reference

No Reference

Location

The Zynq_PL_NostrumNoC_node virtual platform is located in an Imperas/OVP installation at the VLNV: safepower.ovpworld.org / module / Zynq_PL_NostrumNoC_node / 1.0.

Platform Summary

Table : Components in platform

TypeInstanceVendorComponent
Processorcpuxilinx.ovpworld.orgmicroblaze
Peripheralgpioxilinx.ovpworld.orgaxi-gpio
Peripheralnodesafepower.ovpworld.orgNostrumNode
MemoryramSovpworld.orgram
BuspBus(builtin)address width:32
BusgpiodprBus(builtin)address width:32
BridgegpiodprBridge(builtin)

Platform Simulation Attributes

Table 1: Platform Simulation Attributes

AttributeValueDescription
stoponctrlcstoponctrlcStop on control-C



External Ports for Module Zynq_PL_NostrumNoC_node

Table 2: External Ports

Port TypePort NameInternal Connection
busportgpiodprPortgpiodprBus
netportsyncInPortsyncIn
netportsyncOutPortsyncOut
netportgpio_outPgpio_out
netportgpio2_outPgpio2_out
netportgpio_inPgpio_in
netportgpio2_inPgpio2_in
packetnetportnetworkNodePortnetworkNode



Processor [xilinx.ovpworld.org/processor/microblaze/1.0] instance: cpu

Instance Parameters

Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu' it has been instanced with the following parameters:

Table 3: Processor Instance 'cpu' Parameters (Configurations)

ParameterValueDescription
mips100The nominal MIPS for the processor

Memory Map for processor 'cpu' bus: 'pBus'

Processor instance 'cpu' is connected to bus 'pBus' using master port 'INSTRUCTION'.

Processor instance 'cpu' is connected to bus 'pBus' using master port 'DATA'.

Table 4: Memory Map ( 'cpu' / 'pBus' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x00x3FFFFFFramSram
0x400000000x400001FFgpioaxi-gpio
0x410000000x410001FFgpiodprBridgebridge
0x700200000x7003FFFFnodeNostrumNode

Table 5: Bridged Memory Map ( 'cpu' / 'gpiodprBridge' / 'gpiodprBus' [width: 32] )

Lo AddressHi AddressInstanceComponent

Net Connections to processor: 'cpu'

There are no nets connected to this processor.



Peripheral Instances



Peripheral [xilinx.ovpworld.org/peripheral/axi-gpio/1.0] instance: gpio

Description

Xilinx AXI General Purpose IO

Licensing

Open Source Apache 2.0

Limitations

This model implements the AXI GPIO

Reference

pg144-axi-gpio Vivado Design Suite October 5, 2016

There are no configuration options set for this peripheral instance.



Peripheral [safepower.ovpworld.org/peripheral/NostrumNode/1.0] instance: node

Reference

Generated using the VHDL file generic_interface_to_noc_static.vhd provided as part of example December release.

Licensing

Open Source Apache 2.0

Limitations

This model implements the Nostrum NoC node processor interface. It does not model any timing in the transfer of messages between nodes.

Description

The Nostrum Network on Chip (NoC) node peripheral for SafePower Project

Table 6: Configuration options (attributes) set for instance 'node'

AttributesValue
idnocid
generateSync
sendChannelSize
mboxSize




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