Video Link: OpenHW CORE-V Verification Test Bench - Commercial Quality Verification of Open-Source RISC-V Core


OpenHW Group presentation on "CORE-V Verification Test Bench - Commercial Quality Verification of Open-Source RISC-V Core" by Rick OConnor, CEO at OpenHW Group, Aimee Sutton, Engineer at Metrics Technologies, and Simon Davidmann, CEO at Imperas Software, at the RISC-V Global Forum during the virtual event on September 3 2020.

High quality verification is crucial to any HW IP development and in particular for open-source processor cores. Industry quality, coverage driven verification is essential and it is leveraging commercial tools, flows and simulators. These are "must haves" in order for open-source IP to be adopted by leading semiconductor companies for use in high volume SoCs.

This talk provides details of the CORE-V Verification Test Bench, an open-source "step & compare" System Verilog / UVM environment built by the OpenHW Group ecosystem leveraging the Imperas RISC-V Golden Reference Model and the Metrics Cloud-based EDA Platform.

This RISC-V Global Forum presentation can be viewed on the YouTube channel for RISC-V here.