Video Link: OpenHW TV Episode 1: RISC-V Processor Verification


The first episode of OpenHW TV focused on the Verification of CORE-V open source RISC V processor IP cores. Guests include the new Co-Chairs of the OpenHW verification task group (Futurewei and SiliconLabs) with contributing members Imperas Software and Metrics Technologies highlighting the open CORE-V processor IP Design Verification (DV) plan using state of the art flows and SystemVerilog UVM testbenches with encapsulated Imperas RISC-V reference model, coverage-based flow, and Metrics flexible cloud-based environment. Includes a Q&A session after the updates and presentations.

The video can be viewed here.