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1 November 2020 - 10:57am — Model

This core was initially developed as part of the PULP platform under the name Zero-riscy, and has been contributed to lowRISC who maintains it and develops it further. It is under active development, with further code cleanups, feature additions, and test and verification planned for the future.

Processor Model Variants of lowRISC / Ibex_RV32 /

Processor Model Variant: lowRISC / Ibex_RV32 / Ibex_RV32IC
Processor Model Variant: lowRISC / Ibex_RV32 / Ibex_RV32IMC
Processor Model Variant: lowRISC / Ibex_RV32 / Ibex_RV32EC
Processor Model Variant: lowRISC / Ibex_RV32 / Ibex_RV32EMC

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-- The Lost Art Of Processor Verification
-- Speeding Up AI With Vector Instructions
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-- Imperas releases new RISC-V Processor Verification IP to drive RISC-V adoption forward with a flexible methodology for all SoC adopters
-- Silicon Labs selects Imperas RISC-V Reference Model for verification
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Views and Blogs

-- The Lost Art Of Processor Verification
-- RISC-V Verification Challenges Spread
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Industry Events

-- Imperas at 3rd Annual RISC-V Summit, December 8-10 2020
-- Imperas on OpenHW TV episode #5 - Update on Processor Verification, October 29 2020
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