Content for OVP Fast Processor Model Variant: Andes / N25F

APPLICATION NOTES
(more docs)
DOWNLOAD REFERENCE/DEMO PLATFORMS

here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions).
This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Parallel Simulation using Imperas QuantumLeap


Traditionally, processor models and simulators make use of one thread on the host PC.
Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance.
To find out about the Imperas parallel simulation lookup Imperas QuantumLeap.
There are videos of QuantumLeap on ARM here,
and MIPS here.
For press information related to QuantumLeap for ARM click here
or for MIPS click here.
Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.

Embedded Software Development tools


This model executes instructions of the target architecture and provides an interface for debug access.
An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface.
For more information watch the OVP video here.

The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Instruction Set Simulator (ISS) for Andes N25F


An ISS is a software development tool that takes in instructions for a target processor and executes them.
The heart of an ISS is the model of the processor.
Imperas has developed a range of ISS products for use in embedded software development that utilize this fast Fast Processor Model.
The Imperas Andes N25F ISS runs on Windows/Linux x86 systems and takes a cross compiled elf file of your program and allows very fast execution.
The Andes N25F ISS also provides access to standard GDB/RSP debuggers and connects to the Eclipse IDE and
Imperas debuggers.

Overview of Andes N25F Fast Processor Model


Model Variant name: N25F
Description:
    RISC-V N25F 32-bit processor model
Licensing:
    This Model is released under the Open Source Apache 2.0
Extensions Enabled by Default:
    The model has the following architectural extensions enabled, and the following bits in the misa CSR Extensions field will be set upon reset:
    misa bit 0: extension A (atomic instructions)
    misa bit 2: extension C (compressed instructions)
    misa bit 3: extension D (double-precision floating point)
    misa bit 5: extension F (single-precision floating point)
    misa bit 8: RV32I/RV64I/RV128I base integer instruction set
    misa bit 12: extension M (integer multiply/divide instructions)
    misa bit 20: extension U (User mode)
    misa bit 23: extension X (non-standard extensions present)
    To specify features that can be dynamically enabled or disabled by writes to the misa register in addition to those listed above, use parameter "add_Extensions_mask". This is a string parameter containing the feature letters to add; for example, value "DV" indicates that double-precision floating point and the Vector Extension can be enabled or disabled by writes to the misa register, if supported on this variant.
    Legacy parameter "misa_Extensions_mask" can also be used. This Uns32-valued parameter specifies all writable bits in the misa Extensions field, replacing any permitted bits defined in the base variant.
    Note that any features that are indicated as present in the misa mask but absent in the misa will be ignored. See the next section.
Available Extensions Not Enabled by Default:
    The following extensions are supported by the model, but not enabled by default in this variant:
    misa bit 1: extension B (bit manipulation extension)
    misa bit 4: RV32E base integer instruction set (embedded)
    misa bit 7: extension H (hypervisor)
    misa bit 10: extension K (cryptographic)
    misa bit 13: extension N (user-level interrupts)
    misa bit 18: extension S (Supervisor mode)
    misa bit 21: extension V (vector extension)
    To add features from this list to the base variant, use parameter "add_Extensions". This is a string parameter containing the feature letters to add; for example, value "DV" indicates that double-precision floating point and the Vector Extension should be enabled, if they are currently absent and are available on this variant.
    Legacy parameter "misa_Extensions" can also be used. This Uns32-valued parameter specifies the reset value for the misa CSR Extensions field, replacing any permitted bits defined in the base variant.
General Features:
    On this variant, the Machine trap-vector base-address register (mtvec) is writable. It can instead be configured as read-only using parameter "mtvec_is_ro".
    Values written to "mtvec" are masked using the value 0xfffffffd. A different mask of writable bits may be specified using parameter "mtvec_mask" if required. In addition, when Vectored interrupt mode is enabled, parameter "tvec_align" may be used to specify additional hardware-enforced base address alignment. In this variant, "tvec_align" defaults to 0, implying no alignment constraint.
    The initial value of "mtvec" is 0x0. A different value may be specified using parameter "mtvec" if required.
    On reset, the model will restart at address 0x0. A different reset address may be specified using parameter "reset_address" or applied using optional input port "reset_addr" if required.
    On an NMI, the model will restart at address 0x0. A different NMI address may be specified using parameter "nmi_address" or applied using optional input port "nmi_addr" if required.
    WFI will halt the processor until an interrupt occurs. It can instead be configured as a NOP using parameter "wfi_is_nop". WFI timeout wait is implemented with a time limit of 0 (i.e. WFI causes an Illegal Instruction trap in Supervisor mode when mstatus.TW=1).
    The "cycle" CSR is implemented in this variant. Set parameter "cycle_undefined" to True to instead specify that "cycle" is unimplemented and reads of it should trap to Machine mode.
    The "time" CSR is implemented in this variant. Set parameter "time_undefined" to True to instead specify that "time" is unimplemented and reads of it should trap to Machine mode. Usually, the value of the "time" CSR should be provided by the platform - see notes below about the artifact "CSR" bus for information about how this is done.
    The "instret" CSR is implemented in this variant. Set parameter "instret_undefined" to True to instead specify that "instret" is unimplemented and reads of it should trap to Machine mode.
    Unaligned memory accesses are not supported by this variant. Set parameter "unaligned" to "T" to enable such accesses.
    Unaligned memory accesses are not supported for AMO instructions by this variant. Set parameter "unalignedAMO" to "T" to enable such accesses.
    A PMP unit is not implemented by this variant. Set parameter "PMP_registers" to indicate that the unit should be implemented with that number of PMP entries.
    LR/SC instructions are implemented with a 1-byte reservation granule. A different granule size may be specified using parameter "lr_sc_grain".
Floating Point Features:
    The D extension is enabled in this variant independently of the F extension. Set parameter "d_requires_f"to "T" to specify that the D extension requires the F extension to be enabled.
    Half precision floating point is not implemented. Use parameter "Zfh" to enable this if required.
    By default, the processor starts with floating-point instructions disabled (mstatus.FS=0). Use parameter "mstatus_FS" to force mstatus.FS to a non-zero value for floating-point to be enabled from the start.
    The specification is imprecise regarding the conditions under which mstatus.FS is set to Dirty state (3). Parameter "mstatus_fs_mode" can be used to specify the required behavior in this model, as described below.
    If "mstatus_fs_mode" is set to "always_dirty" then the model implements a simplified floating point status view in which mstatus.FS holds values 0 (Off) and 3 (Dirty) only; any write of values 1 (Initial) or 2 (Clean) from privileged code behave as if value 3 was written.
    If "mstatus_fs_mode" is set to "write_1" then mstatus.FS will be set to 3 (Dirty) by any explicit write to the fflags, frm or fcsr control registers, or by any executed instruction that writes an FPR, or by any executed floating point compare or conversion to integer/unsigned that signals a floating point exception. Floating point compare or conversion to integer/unsigned instructions that do not signal an exception will not set mstatus.FS.
    If "mstatus_fs_mode" is set to "write_any" then mstatus.FS will be set to 3 (Dirty) by any explicit write to the fflags, frm or fcsr control registers, or by any executed instruction that writes an FPR, or by any executed floating point compare or conversion even if those instructions do not signal a floating point exception.
    In this variant, "mstatus_fs_mode" is set to "write_1".
CLIC:
    The model can be configured to implement a Core Local Interrupt Controller (CLIC) using parameter "CLICLEVELS"; when non-zero, the CLIC is present with the specified number of interrupt levels (2-256), as described in the RISC-V Core-Local Interrupt Controller specification, and further parameters are made available to configure other aspects of the CLIC. "CLICLEVELS" is zero in this variant, indicating that a CLIC is not implemented.
Load-Reserved/Store-Conditional Locking:
    By default, LR/SC locking is implemented automatically by the model and simulator, with a reservation granule defined by the "lr_sc_grain" parameter. It is also possible to implement locking externally to the model in a platform component, using the "LR_address", "SC_address" and "SC_valid" net ports, as described below.
    The "LR_address" output net port is written by the model with the address used by a load-reserved instruction as it executes. This port should be connected as an input to the external lock management component, which should record the address, and also that an LR/SC transaction is active.
    The "SC_address" output net port is written by the model with the address used by a store-conditional instruction as it executes. This should be connected as an input to the external lock management component, which should compare the address with the previously-recorded load-reserved address, and determine from this (and other implementation-specific constraints) whether the store should succeed. It should then immediately write the Boolean success/fail code to the "SC_valid" input net port of the model. Finally, it should update state to indicate that an LR/SC transaction is no longer active.
    It is also possible to write zero to the "SC_valid" input net port at any time outside the context of a store-conditional instruction, which will mark any active LR/SC transaction as invalid.
    Irrespective of whether LR/SC locking is implemented internally or externally, taking any exception or interrupt or executing exception-return instructions (e.g. MRET) will always mark any active LR/SC transaction as invalid.
Active Atomic Operation Indication:
    The "AMO_active" output net port is written by the model with a code indicating any current atomic memory operation while the instruction is active. The written codes are:
    0: no atomic instruction active
    1: AMOMIN active
    2: AMOMAX active
    3: AMOMINU active
    4: AMOMAXU active
    5: AMOADD active
    6: AMOXOR active
    7: AMOOR active
    8: AMOAND active
    9: AMOSWAP active
    10: LR active
    11: SC active
Interrupts:
    The "reset" port is an active-high reset input. The processor is halted when "reset" goes high and resumes execution from the reset address specified using the "reset_address" parameter or "reset_addr" port when the signal goes low. The "mcause" register is cleared to zero.
    The "nmi" port is an active-high NMI input. The processor resumes execution from the address specified using the "nmi_address" parameter or "nmi_addr" port when the NMI signal goes high. The "mcause" register is cleared to zero.
    All other interrupt ports are active high. For each implemented privileged execution level, there are by default input ports for software interrupt, timer interrupt and external interrupt; for example, for Machine mode, these are called "MSWInterrupt", "MTimerInterrupt" and "MExternalInterrupt", respectively. When the N extension is implemented, ports are also present for User mode. Parameter "unimp_int_mask" allows the default behavior to be changed to exclude certain interrupt ports. The parameter value is a mask in the same format as the "mip" CSR; any interrupt corresponding to a non-zero bit in this mask will be removed from the processor and read as zero in "mip", "mie" and "mideleg" CSRs (and Supervisor and User mode equivalents if implemented).
    Parameter "external_int_id" can be used to enable extra interrupt ID input ports on each hart. If the parameter is True then when an external interrupt is applied the value on the ID port is sampled and used to fill the Exception Code field in the "mcause" CSR (or the equivalent CSR for other execution levels). For Machine mode, the extra interrupt ID port is called "MExternalInterruptID".
    The "deferint" port is an active-high artifact input that, when written to 1, prevents any pending-and-enabled interrupt being taken (normally, such an interrupt would be taken on the next instruction after it becomes pending-and-enabled). The purpose of this signal is to enable alignment with hardware models in step-and-compare usage.
Debug Mode:
    The model can be configured to implement Debug mode using parameter "debug_mode". This implements features described in Chapter 4 of the RISC-V External Debug Support specification with version specified by parameter "debug_version" (see References). Some aspects of this mode are not defined in the specification because they are implementation-specific; the model provides infrastructure to allow implementation of a Debug Module using a custom harness. Features added are described below.
    Parameter "debug_mode" can be used to specify three different behaviors, as follows:
    1. If set to value "vector", then operations that would cause entry to Debug mode result in the processor jumping to the address specified by the "debug_address" parameter. It will execute at this address, in Debug mode, until a "dret" instruction causes return to non-Debug mode. Any exception generated during this execution will cause a jump to the address specified by the "dexc_address" parameter.
    2. If set to value "interrupt", then operations that would cause entry to Debug mode result in the processor simulation call (e.g. opProcessorSimulate) returning, with a stop reason of OP_SR_INTERRUPT. In this usage scenario, the Debug Module is implemented in the simulation harness.
    3. If set to value "halt", then operations that would cause entry to Debug mode result in the processor halting. Depending on the simulation environment, this might cause a return from the simulation call with a stop reason of OP_SR_HALT, or debug mode might be implemented by another platform component which then restarts the debugged processor again.
Debug State Entry:
    The specification does not define how Debug mode is implemented. In this model, Debug mode is enabled by a Boolean pseudo-register, "DM". When "DM" is True, the processor is in Debug mode. When "DM" is False, mode is defined by "mstatus" in the usual way.
    Entry to Debug mode can be performed in any of these ways:
    1. By writing True to register "DM" (e.g. using opProcessorRegWrite) followed by simulation of at least one cycle (e.g. using opProcessorSimulate), dcsr cause will be reported as trigger;
    2. By writing a 1 then 0 to net "haltreq" (using opNetWrite) followed by simulation of at least one cycle (e.g. using opProcessorSimulate);
    3. By writing a 1 to net "resethaltreq" (using opNetWrite) while the "reset" signal undergoes a negedge transition, followed by simulation of at least one cycle (e.g. using opProcessorSimulate);
    4. By executing an "ebreak" instruction when Debug mode entry for the current processor mode is enabled by dcsr.ebreakm, dcsr.ebreaks or dcsr.ebreaku.
    In all cases, the processor will save required state in "dpc" and "dcsr" and then perform actions described above, depending in the value of the "debug_mode" parameter.
Debug State Exit:
    Exit from Debug mode can be performed in any of these ways:
    1. By writing False to register "DM" (e.g. using opProcessorRegWrite) followed by simulation of at least one cycle (e.g. using opProcessorSimulate);
    2. By executing an "dret" instruction when Debug mode.
    In both cases, the processor will perform the steps described in section 4.6 (Resume) of the Debug specification.
Debug Registers:
    When Debug mode is enabled, registers "dcsr", "dpc", "dscratch0" and "dscratch1" are implemented as described in the specification. These may be manipulated externally by a Debug Module using opProcessorRegRead or opProcessorRegWrite; for example, the Debug Module could write "dcsr" to enable "ebreak" instruction behavior as described above, or read and write "dpc" to emulate stepping over an "ebreak" instruction prior to resumption from Debug mode.
Debug Mode Execution:
    The specification allows execution of code fragments in Debug mode. A Debug Module implementation can cause execution in Debug mode by the following steps:
    1. Write the address of a Program Buffer to the program counter using opProcessorPCSet;
    2. If "debug_mode" is set to "halt", write 0 to pseudo-register "DMStall" (to leave halted state);
    3. If entry to Debug mode was handled by exiting the simulation callback, call opProcessorSimulate or opRootModuleSimulate to resume simulation.
    Debug mode will be re-entered in these cases:
    1. By execution of an "ebreak" instruction; or:
    2. By execution of an instruction that causes an exception.
    In both cases, the processor will either jump to the debug exception address, or return control immediately to the harness, with stopReason of OP_SR_INTERRUPT, or perform a halt, depending on the value of the "debug_mode" parameter.
Debug Single Step:
    When in Debug mode, the processor or harness can cause a single instruction to be executed on return from that mode by setting dcsr.step. After one non-Debug-mode instruction has been executed, control will be returned to the harness. The processor will remain in single-step mode until dcsr.step is cleared.
Debug Ports:
    Port "DM" is an output signal that indicates whether the processor is in Debug mode
    Port "haltreq" is a rising-edge-triggered signal that triggers entry to Debug mode (see above).
    Port "resethaltreq" is a level-sensitive signal that triggers entry to Debug mode after reset (see above).
Trigger Module:
    This model is configured with a trigger module, implementing a subset of the behavior described in Chapter 5 of the RISC-V External Debug Support specification with version specified by parameter "debug_version" (see References).
Trigger Module Restrictions:
    The model currently supports tdata1 of type 0, type 2 (mcontrol), type 3 (icount), type 4 (itrigger), type 5 (etrigger) and type 6 (mcontrol6). icount triggers are implemented for a single instruction only, with count hard-wired to 1 and automatic zeroing of mode bits when the trigger fires.
Trigger Module Parameters:
    Parameter "trigger_num" is used to specify the number of implemented triggers. In this variant, "trigger_num" is 4.
    Parameter "tinfo" is used to specify the value of the read-only "tinfo" register, which indicates the trigger types supported. In this variant, "tinfo" is 0x3d.
    Parameter "tinfo_undefined" is used to specify whether the "tinfo" register is undefined, in which case reads of it trap to Machine mode. In this variant, "tinfo_undefined" is 0.
    Parameter "tcontrol_undefined" is used to specify whether the "tcontrol" register is undefined, in which case accesses to it trap to Machine mode. In this variant, "tcontrol_undefined" is 0.
    Parameter "mcontext_undefined" is used to specify whether the "mcontext" register is undefined, in which case accesses to it trap to Machine mode. In this variant, "mcontext_undefined" is 0.
    Parameter "scontext_undefined" is used to specify whether the "scontext" register is undefined, in which case accesses to it trap to Machine mode. In this variant, "scontext_undefined" is 0.
    Parameter "amo_trigger" is used to specify whether load/store triggers are activated for AMO instructions. In this variant, "amo_trigger" is 0.
    Parameter "no_hit" is used to specify whether the "hit" bit in tdata1 is unimplemented. In this variant, "no_hit" is 0.
    Parameter "mcontext_bits" is used to specify the number of writable bits in the "mcontext" register. In this variant, "mcontext_bits" is 6.
    Parameter "mvalue_bits" is used to specify the number of writable bits in the "mvalue" field in "textra32"/"textra64" registers; if zero, the "mselect" field is tied to zero. In this variant, "mvalue_bits" is 6.
    Parameter "mcontrol_maskmax" is used to specify the value of field "maskmax" in the "mcontrol" register. In this variant, "mcontrol_maskmax" is 63.
Debug Mask:
    It is possible to enable model debug messages in various categories. This can be done statically using the "override_debugMask" parameter, or dynamically using the "debugflags" command. Enabled messages are specified using a bitmask value, as follows:
    Value 0x002: enable debugging of PMP and virtual memory state;
    Value 0x004: enable debugging of interrupt state.
    All other bits in the debug bitmask are reserved and must not be set to non-zero values.
Integration Support:
    This model implements a number of non-architectural pseudo-registers and other features to facilitate integration.
CSR Register External Implementation:
    If parameter "enable_CSR_bus" is True, an artifact 16-bit bus "CSR" is enabled. Slave callbacks installed on this bus can be used to implement modified CSR behavior (use opBusSlaveNew or icmMapExternalMemory, depending on the client API). A CSR with index 0xABC is mapped on the bus at address 0xABC0; as a concrete example, implementing CSR "time" (number 0xC01) externally requires installation of callbacks at address 0xC010 on the CSR bus.
LR/SC Active Address:
    Artifact register "LRSCAddress" shows the active LR/SC lock address. The register holds all-ones if there is no LR/SC operation active or if LR/SC locking is implemented externally as described above.
Limitations:
    Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately. This means that instruction barrier instructions (e.g. fence.i) are treated as NOPs, with the exception of any Illegal Instruction behavior, which is modeled.
    Caches and write buffers are not modeled in any way. All loads, fetches and stores complete immediately and in order, and are fully synchronous. Data barrier instructions (e.g. fence) are treated as NOPs, with the exception of any Illegal Instruction behavior, which is modeled.
    Real-world timing effects are not modeled: all instructions are assumed to complete in a single cycle.
    Hardware Performance Monitor registers are not implemented and hardwired to zero.
    Andes-specific cache, local memory and ECC behavior is not yet implemented, except for CSR state.
    Andes Performance and Code Dense instructions and associated CSR state are implemented, but the EXEC.IT instruction supports in-memory table mode using the uitb CSR only (not hardwired mode).
    PMP and PMA accesses that any-byte match but do not all-byte match are broken into separate smaller accesses that follow all-byte match rules.
Verification:
    All instructions have been extensively tested by Imperas, using tests generated specifically for this model and also reference tests from https://github.com/riscv/riscv-tests.
    Also reference tests have been used from various sources including:
    https://github.com/riscv/riscv-tests
    https://github.com/ucb-bar/riscv-torture
    The Imperas OVPsim RISC-V models are used in the RISC-V Foundation Compliance Framework as a functional Golden Reference:
    https://github.com/riscv/riscv-compliance
    where the simulated model is used to provide the reference signatures for compliance testing. The Imperas OVPsim RISC-V models are used as reference in both open source and commercial instruction stream test generators for hardware design verification, for example:
    http://valtrix.in/sting from Valtrix
    https://github.com/google/riscv-dv from Google
    The Imperas OVPsim RISC-V models are also used by commercial and open source RISC-V Core RTL developers as a reference to ensure correct functionality of their IP.
References:
    The Model details are based upon the following specifications:
    RISC-V Instruction Set Manual, Volume I: User-Level ISA (User Architecture Version 2.2)
    RISC-V Instruction Set Manual, Volume II: Privileged Architecture (Privileged Architecture Version 1.10)
    ---- AndesCore_N25_DS130_V1.0 DS130-10
    ---- AndeStar V5 Architecture and CSR Definitions (UM164-1515, 2020-05-08)
Andes-Specific Extensions:
    Andes processors add various custom extensions to the basic RISC-V architecture. This model implements the following:
    1: Hardware Stack Protection (if mmsc_cfg.HSP=1);
    2: Physical Memory Attribute Unit (if mmsc_cfg.DPMA=1).
    3: Performance Throttling (register interface only, if mmsc_cfg.PFT=1);
    4: CSRs for CCTL Operations (register interface only, if mmsc_cfg.CCTLCSR=1);
    5: Performance Extension instructions (if mmsc_cfg.EV5MPE=1);
    6: CodeDense instructions (if mmsc_cfg.ECD=1);
    7: Half-precision load/store instructions (if mmsc_cfg.EFHW=1).
    8: BFLOAT16 conversion instructions (if mmsc_cfg.BFLOAT16=1).
    9: Half-precision arithmetic instructions (if mmsc_cfg.ZFH=1).
    10: Vector INT4 load extension (if mmsc_cfg.VL4=1).
    Other Andes-specific extensions are not currently modeled. The exact set of supported extensions can be configured using parameter "andesExtensions/mmsc_cfg", which overrides the default value of the mmsc_cfg register (see detailed description below).
Andes-Specific Parameters:
    In addition to the base model RISC-V parameters, this model implements parameters allowing Andes-specific model features to be controlled. These parameters are documented below.
Parameter andesExtensions/mmsc_cfg:
    This parameter allows the value of the read-only mmsc_cfg register to be specified. Bits that affect behavior of the model are:
    bit 3 (ECD): enables CodeDense instructions and uitb CSR.
    bit 4 (PFT): determines presence of mpft_ctl register and affects implemented fields in mxstatus.
    bit 5 (HSP): enables HW Stack protection, relevant CSRs and affects implemented fields in mxstatus.
    bit 13 (EV5PE): enables Performance Extension support.
    bit 15 (PMNDS): enables Andes-enhanced Performance Monitoring.
    bit 16 (CCTLCSR): enables CCTL CSRs.
    bit 30 (DPMA): enables the Physical Memory Attribute Unit and relevant CSRs.
    bit 32 (BF16CVT): enables BFLOAT16 conversion extension.
    bit 33 (ZFH): enables FP16 half-precision extension.
    bit 34 (VL4): enables vector INT4 load extension.
    Other bits can be set or cleared but do not affect model behavior.
    Example: --override iss/cpu0/andesExtensions/mmsc_cfg=0x2028
Parameter andesExtensions/micm_cfg:
    This parameter allows the value of the read-only micm_cfg register to be specified. Bits that affect behavior of the model are:
    bits 8:6 (ISZ): enables mcache_ctl CSR if non-zero.
    bits 14:12 (ILMB): enables milmb CSR if non-zero.
    Other bits can be set or cleared but do not affect model behavior, except that if any bit is non zero then IME/PIME bits in mxstatus are modeled.
    Example: --override iss/cpu0/andesExtensions/micm_cfg=0
Parameter andesExtensions/mdcm_cfg:
    This parameter allows the value of the read-only mdcm_cfg register to be specified. Bits that affect behavior of the model are:
    bits 8:6 (DSZ): enables mcache_ctl CSR if non-zero.
    bits 14:12 (DLMB): enables mdlmb CSR if non-zero.
    Other bits can be set or cleared but do not affect model behavior, except that if any bit is non zero then DME/DIME bits in mxstatus are modeled.
    Example: --override iss/cpu0/andesExtensions/mdcm_cfg=0
Parameter andesExtensions/uitb:
    This parameter allows the value of the uitb register to be specified.
    Example: --override iss/cpu0/andesExtensions/uitb=0
Parameter andesExtensions/milmb:
    This parameter allows the value of the milmb register to be specified.
    Example: --override iss/cpu0/andesExtensions/milmb=0
Parameter andesExtensions/milmbMask:
    This parameter allows the mask of writable bits in the milmb register to be specified. The default value for this variant is 0xe (RWECC and ECCEN are writable, all other bits are read-only).
    Example: --override iss/cpu0/andesExtensions/milmbMask=0xe
Parameter andesExtensions/mdlmb:
    This parameter allows the value of the mdlmb register to be specified.
    Example: --override iss/cpu0/andesExtensions/mdlmb=0
Parameter andesExtensions/mdlmbMask:
    This parameter allows the mask of writable bits in the mdlmb register to be specified. The default value for this variant is 0xe (RWECC and ECCEN are writable, all other bits are read-only).
    Example: --override iss/cpu0/andesExtensions/mdlmbMask=0xe
Parameter andesExtensions/PMA_grain:
    This parameter allows the grain size of Physical Memory Attribute regions to be specified. The default value for this variant is 0, meaning that PMA regions as small as 4 bytes are implemented.
    Example: --override iss/cpu0/andesExtensions/PMA_grain=16
Hardware Stack Protection:
    Hardware Stack Protection is present on this variant (mmsc_cfg.HSP=1). Registers mhsp_ctl, msp_bound and msp_base are implemented.
Physical Memory Attribute Unit:
    The Physical Memory Attribute Unit is not present on this variant (mmsc_cfg.DPMA=0).
Performance Throttling:
    Performance Throttling registers are present on this variant (mmsc_cfg.PFT=1). Register mpft_ctl is present but has no behavior except for the effects on mxstatus, which are modeled.
Andes-Enhanced Performance Monitoring:
    Andes-Enhanced Performance Monitoring is present on this variant (mmsc_cfg.PMNDS=1).
CSRs for CCTL Operations:
    CSRs for CCTL Operation are not present on this variant (mmsc_cfg.CCTLCSR=0).
Andes-Specific Instructions:
    This section describes Andes-specific instructions implemented by this variant. Refer to Andes reference documentation for more information.
Performance Extension Instructions:
    ADDIGP
    BBC
    BBS
    BEQC
    BNEC
    BFOS
    BFOZ
    LEA.h
    LEA.w
    LEA.d
    LBGP
    LBUGP
    LHGP
    LHUGP
    LWGP
    SBGP
    SHGP
    SWGP
    FFB
    FFZMISM
    FFMISM
    FLMISM
CodeDense Instructions:
    EXEC.IT
    EX9.IT

Model downloadable (needs registration and to be logged in) in package andes_riscv.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant N25F is available OVP_Model_Specific_Information_andes_riscv_N25F.pdf.

Configuration


Location: The Fast Processor Model source and object file is found in the installation VLNV tree: andes.ovpworld.org/processor/riscv/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0xf3
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.

TLM Initiator Ports (Bus Ports)


Port Type Name Width (bits) Description
master INSTRUCTION 32
master DATA 32

SystemC Signal Ports (Net Ports)


Port Type Name Description
reset input
reset_addr input
nmi input
nmi_addr input
MSWInterrupt input
MTimerInterrupt input
MExternalInterrupt input
irq_ack_o output
irq_id_o output
sec_lvl_o output
LR_address output
SC_address output
SC_valid input
AMO_active output
deferint input

No FIFO Ports in N25F.


Exceptions


Name Code Description
InstructionAddressMisaligned 0
InstructionAccessFault 1
IllegalInstruction 2
Breakpoint 3
LoadAddressMisaligned 4
LoadAccessFault 5
StoreAMOAddressMisaligned 6
StoreAMOAccessFault 7
EnvironmentCallFromUMode 8
EnvironmentCallFromMMode 11
InstructionPageFault 12
LoadPageFault 13
StoreAMOPageFault 15
HSP_OVF 32
HSP_UDF 33
MSWInterrupt 67
MTimerInterrupt 71
MExternalInterrupt 75

Execution Modes


Mode Code Description
User 0
Machine 3

More Detailed Information

The N25F OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_andes_riscv_N25F.pdf.

Other Sites/Pages with similar information

Information on the N25F OVP Fast Processor Model can also be found on other web sites::
www.imperas.com has more information on the model library.