Content for OVP Fast Processor Model Variant: MIPS / interAptiv

DOWNLOAD MODEL Packages for Model: interAptiv Tool Chain (GCC,GDB): MIPS MODEL INFORMATION Model Information Detailed Documentation: interAptiv LICENSING (USING THE MODEL) Legal License Agreement Getting a FLEXlm license key SUPPORT FORUMS Model Specific Support: MIPS General VIDEOS Sketch Cartoon Introduction to Imperas Continuous Integration and Test Automation with Jenkins MIPS Demo Video Presentation MIPS Malta Linux Video 1) - Installing OVPsim simulator, MIPS Malta Platform and Booting Linux (boots in 4 seconds) MIPS Malta Linux Video 2)- Installing, creating full disk image and booting multiuser Linux MIPS Malta Linux Video 3) - Cross compiling user applications and debugging them on simulated MIPS Linux Hetero 1xARM7 3xMIPS32LE Demonstration Video 64 Bit and Multiple Quad Core Processors Video Demonstration MIPS core models and QuantumLeap Parallel Simulation using multi-core host PC gaining significant simulation speed. Application Development and Debug using GDB / Eclipse Demonstration Video RISC-V Custom Instruction Design and Verification Flow Altera Nios II Bare Metal & Cyclone III Linux Booting Demo Video ARM Extendable Platform Kits and Tools Demo Video Using the ARM DS-5 Debugger with Imperas simulators and models demonstration video Using the Green Hills Software MULTI Debugger with Imperas simulators and models demonstration video on this link. ">DVCon 2021. A personal perspective on the history of SystemVerilog and Superlog Imperas CEO Simon Davidmann Introducing Imperas Software Information on Imperas at ARM TechCon 2016 DVCon 2021. 25 years after Verisity, verification is still evolving Customer case study for AUDI Nira with the Imperas Solution of Software Testing in Automotive (more videos) PRESENTATIONS MIPS Demo Slide Presentation Introduction to Open Virtual Platforms (OVP) Open Virtual Platforms - Ecosystem (more) APPLICATION NOTES (more docs)

DOWNLOAD REFERENCE/DEMO PLATFORMS Examples for MIPS Aptiv Self contained ARM examples utilizing the ARM AArch64 ARMv8 architecture Main OVP Download including OVPsim Simulator and Self Contained Examples of all CPU Models using The 1074K bare metal platforms and examples Malta Platform using microMIPS running linux M14K bare metal platforms and examples Malta Platform using microMIPS running linux Malta Platform booting Linux2.6 Malta Platform booting Nucleus SystemC TLM2.0 MIPS Malta Platform running linux Malta Platform Downloading Full Linux Distribution Self contained MIPS64 Examples Self contained MIPS32 Examples Malta Platform booting Linux2.6 Malta Platform booting Nucleus Malta Platform Downloading Full Linux Distribution ARM7 and MIPS32 hetero multicore Versatile Express booting Linux on Cortex-A9MP Single, Dual and Quad Core Platform including ARM Cortex-A9MPx4 to run ARM MPCore Sample Code Versatile Express booting Linux on Cortex-A15MP Single, Dual and Quad Core Versatile Express booting Linux kernels on four Cortex-A15MP Quad Core processors Versatile Express booting Linux on Cortex-A9MP Single, Dual and Quad Core Versatile Express booting Linux on Cortex-A15MP Single, Dual and Quad Core Platform including ARM Cortex-A9MPx4 to run ARM MPCore Sample Code Versatile Express booting Linux kernels on four Cortex-A15MP Quad Core processors GENERAL DOWNLOADS Simulator: OVPsim Compiling Peripheral (PSE) Tool Chain (GCC,GDB) EXTERNAL DOWNLOADS Compiling Platforms Tool Chain (Msys/MinGW) Eclipse IDE GENERAL DOCUMENTATION Installation & Getting started Building & Simulating OVP Platforms Using CPU Models Using with SystemC / TLM2 Debugging with GDB Using the Eclipse IDE with OVP Write peripheral models Creating a CPU Model (advanced) (more docs) TUTORIALS (more tutorials / videos)

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Model Information

This page provides detailed information about the OVP Fast Processor Model of the MIPS interAptiv core.
Processor IP owner is MIPS. More information is available from them here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions).
This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Parallel Simulation using Imperas QuantumLeap

Traditionally, processor models and simulators make use of one thread on the host PC.
Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance.
To find out about the Imperas parallel simulation lookup Imperas QuantumLeap.
There are videos of QuantumLeap on ARM here,
and MIPS here.
For press information related to QuantumLeap for ARM click here
or for MIPS click here.
Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.

Embedded Software Development tools

This model executes instructions of the target architecture and provides an interface for debug access.
An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface.
For more information watch the OVP video here.

The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Instruction Set Simulator (ISS) for MIPS interAptiv

An ISS is a software development tool that takes in instructions for a target processor and executes them.
The heart of an ISS is the model of the processor.
Imperas has developed a range of ISS products for use in embedded software development that utilize this fast Fast Processor Model.
The Imperas MIPS interAptiv ISS runs on Windows/Linux x86 systems and takes a cross compiled elf file of your program and allows very fast execution.
The MIPS interAptiv ISS also provides access to standard GDB/RSP debuggers and connects to the Eclipse IDE and
Imperas debuggers.

Overview of MIPS interAptiv Fast Processor Model

Model Variant name: interAptiv
Description:
    MIPS32 Configurable Processor Model
Licensing:
    Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.
Limitations:
    If this model is not part of your installation, then it is available for download from www.OVPworld.org/ip-vendor-mips.
    Cache model does not implement coherency
Verification:
    Models have been validated correct as part of the MIPS Verified program and run through the MIPS AVP test programs
Features:
    only MIPS32 Instruction set implemented
    MMU Type: Standard TLB
    FPU implemented
    L1 I and D cache model in either full or tag-only mode implemented (disabled by default)
    Segmentation control implemented
    Enhanced virtual address (EVA) supported
    Vectored interrupts implemented
    MIPS16e ASE implemented
    MT ASE implemented
    DSP ASE Rev 2 implemented

Model downloadable (needs registration and to be logged in) in package mips32.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant interAptiv is available OVP_Model_Specific_Information_mips32_r1r5_interAptiv.pdf.

Configuration

Location: The Fast Processor Model source and object file is found in the installation VLNV tree: mips.ovpworld.org/processor/mips32_r1r5/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0x8
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.

TLM Initiator Ports (Bus Ports)

SystemC Signal Ports (Net Ports)

No FIFO Ports in interAptiv.

Exceptions

Execution Modes

More Detailed Information

The interAptiv OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_mips32_r1r5_interAptiv.pdf.

Other Sites/Pages with similar information

Information on the interAptiv OVP Fast Processor Model can also be found on other web sites::
www.imperas.com has more information on the model library.