Virtual Platform Workshop at 46th DAC

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WEDNESDAY July 29, 9:00am - 5:30pm, 2009


WORKSHOP: Virtual Platform Workshop at DAC 2009

Soha Hassoun - Tufts Univ., Medford, MA
Larry Lapides - Imperas Software Ltd., Thame, UK

Virtual Platforms (VPs) have emerged as a cornerstone in SOC design validation and in embedded software development. Virtual platforms, a model representation created by assembling component models, enable early software development and lead to fewer silicon re-spins and shorter time-to-market. This workshop outlined challenges in building and utilizing VPs for software development and verification, and showcased solutions from both vendor and user perspectives. The purpose of this first workshop was to bring together people interested in this topic to promote VPs, educate users about their potential, and to exchange usage experiences. The participants were those interested in various topics associated with VP use and development: IP use, SOC, embedded system, embedded software, and software functional verification.

The workshop began with a tutorial-like state-of-the-art overview on critical issues facing VP developers and users. The morning session then continued with detailed presentations on building VPs: exploring timing mechanisms in TLM (Transaction-Level Modeling), integration of RTL Models into Virtual Platforms for complex multicore systems, and platform composition and refinement. Speakers were from Qualcomm, Inc., Brian Bailey Consulting, Carbon Design Systems, Inc., FZI Karlsruhe, and EVE.

The lunch time panel session was lively, interesting and brought several industry experts together to discuss issues facing virtual platform designers and users such as software reuse, status of VP standards, and how and when VPs will achieve broader acceptance. The panelists were from ARM, Qualcomm, GreenSocs, Open Virtual Platforms (OVP), and Cadence Design Systems, Inc. The lunch panel was moderated by Michael Sanie, Maestro Intl., Menlo Park, CA.

The afternoon session consisted of six industry experts introducing tools and experiences in: software functional verification, architectural exploration on VPs, combining TLM-2.0 code with legacy virtual platforms, and system verification. The speakers were from CoWare, Inc., Intel Corp., Posedge Software, Imperas Ltd., Mentor Graphics, and Synopsys, Inc.

See panel below for the presentations.

Some comments from the organizer (Larry Lapides):
This panel exceeded the expectations of the organizers, presenters and other participants. We had excellent participation from the different interested parties in virtual platforms, namely users, tools providers and IP developers. The topics covered, building virtual platforms and using virtual platforms, and the materials presented showed that while there is still a lot of work to be done in this area, virtual platforms are becoming accepted as part of the necessary methodology for tasks as varied as architecture exploration and software development.

Comments from some of the particpants:

"The panel was actually very good and the panel cast list actually provoked some good informed debate - rather than just opinion and invective."

"an interesting and important workshop."

"Thanks for organizing such a good workshop. We see virtual platforms as an important new technology for the next generation of embedded software development and the workshop was a great place for information gathering."

PresentationsClick to view, right click to download. Presenter in italics.


Virtual Platforms: Challenges and Opportunities Ramesh Chandra, Qualcomm San Diego, CA
Modeling, Analysis And Refinement Of Heterogeneous Interconnected Systems Using Virtual Platforms Oliver Bringmann, FZI Karlsruhe, Joachim Gerlach, Robert Bosch, Ulrich Nageldinger, Infineon Technologies, Jens Stellmacher, Cadence Design Systems
Timing Mechanisms in Transaction Level Models Brian Bailey, consultant, Beaverton, OR
Assembling and Debugging VPs of Complex Multi-core Systems Tom Rathje, Carbon Design Systems, Acton, MA
Integration of RTL Models into Virtual Platforms via Transaction-Based Emulation Ron Choi, EVE, San Jose, CA
Panel: ARM John Goodenough, ARM, San Jose, CA
Panel: OVP Simon Davidmann, Open Virtual Platforms, Thame, UK
Panel: Cadence Jason Andrews, Cadence, Minneapolis, MN
Panel: GreenSocs Mark Burton,, Barcelona, Spain
Panel: Qualcomm Jose Corleto, Qualcomm, San Diego, CA
Getting Started with Virtual Platforms: A Software Developer Perspective Achim Nohl, CoWare, Aachen, Germany
Pre-Silicon USB Driver Development on SystemC Based Virtual Platforms Filip Thoen, Synopsys, Mountain View, CA
Software Verification and Debug Using Virtual Platforms Duncan Graham, Imperas, Thame, UK
Architectural/Micro-architectural Exploration on VPs Qi Zhu, Michael Kishinevsky, Zhu Zhou, Atul Kwatra, Intel Corporation, Hillsboro, OR
TLM Platforms Redefine Hardware Virtualization Jon McDonald, Mentor Graphics, Jacksonville, FL
Software and System Verification for the MIPS Malta Platform Henry Von Bank, Posedge Software, Rogers, MN