Video Link: Valtrix and verification of RISC-V Open ISA cores

Imperas presentation on "Verification of RISC-V Open ISA processors - Testing functional correctness for the latest extensions for Bit Manipulation and Vectors." by Shubhodeep Roy Choudhury, Managing Director & Co-founder at Valtrix Systems, at the RISC-V pavilion during the virtual event for DAC 2020.

The RISC-V Vector extensions are designed to support complex arithmetic operations required for applications involving linear algebra, such as supercomputers, cryptography, AI, ML and deep learning (DL). A traditional or scalar ISA is based around operations on single data items, a Vector processor operates over an array of data items which enables acceleration of key computational workloads.

This talk, presents the different mechanisms and methodologies employed in the design verification flow to test the functional correctness of vector and bit manipulation extensions and interoperability with other extensions and privilege mode of execution in open source and commercial RISC-V designs.

Due to pressures of the market opportunity and potential for RISC-V Vector implementations, RTL level designs are tracking the specification revisions which in turn require the test plan to adapt to the evolving requirements. Latest status updates and results of the current work in progress will be presented.

This DAC presentation can be viewed on the YouTube channel for DAC TV here.