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OVP Peripheral Model: SifivePRCI

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Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

Power Reset Clocking Interrupt (PRCI) block for SiFive FU540 chip

Limitations

Register only model. Reset values based on typical post-ZSBL configuration (1GHz coreclk, 500MHz tlclk).

Licensing

Open Source Apache 2.0

Reference

SiFive Freedom U540-C000 Manual FU540-C000-v1.0.pdf (https://www.sifive.com/documentation/chips/freedom-u540-c000-manual)

Location

The PRCI peripheral model is located in an Imperas/OVP installation at the VLNV: sifive.ovpworld.org / peripheral / PRCI / 1.0.

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Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

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Net Ports

This model has the following net ports:

Table 1: Net Ports

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Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 2: Bus Slave Port: bport1

Table 3: Bus Slave Port: bport1 Registers:

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Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 4: Publicly available platforms using peripheral 'PRCI'