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XilinxZynq_7000Gpio



OVP Peripheral Model: XilinxZynq_7000Gpio



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

Zynq 7000 Platform GPIO Registers (gpio)

Included is the visualization of LED and SW connectivity for the ZC702/ZC706 devices.

Licensing

Open Source Apache 2.0

Limitations

This model implements only the registers for generation of input or output data values.

No interrupt generation is currently included in the model.

Reference

Zynq-7000 TRM (https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf)

Location

The zynq_7000-gpio peripheral model is located in an Imperas/OVP installation at the VLNV: xilinx.ovpworld.org / peripheral / zynq_7000-gpio / 1.0.



Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

NameTypeDescription
configenumerationLED/Switch Board Configuration (zc702/zc706)
swtestboolEnable Switch and LED Test pattern generation



Net Ports

This model has the following net ports:

Table 1: Net Ports

NameTypeMust Be ConnectedDescription
interruptoutputF (False)
gpio_bank0_ininputF (False)
gpio_bank0_outoutputF (False)
gpio_bank1_ininputF (False)
gpio_bank1_outoutputF (False)
gpio_bank2_ininputF (False)
gpio_bank2_outoutputF (False)
gpio_bank2_oen_outoutputF (False)
gpio_bank3_ininputF (False)
gpio_bank3_outoutputF (False)
gpio_bank3_oen_outoutputF (False)
intOutoutputF (False)Interrupt signal



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 2: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x1000T (True)

Table 3: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
REG_MASK_DATA_0_LSW0x032Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
REG_MASK_DATA_0_MSW0x432Maskable Output Data (GPIO Bank0, MIO, Upper 16bits)
REG_MASK_DATA_1_LSW0x832Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)
REG_MASK_DATA_1_MSW0xc32Maskable Output Data (GPIO Bank1, MIO, Upper 6bits)
REG_MASK_DATA_2_LSW0x1032Maskable Output Data (GPIO Bank2, EMIO, Lower 16bits)
REG_MASK_DATA_2_MSW0x1432Maskable Output Data (GPIO Bank2, EMIO, Upper 16bits)
REG_MASK_DATA_3_LSW0x1832Maskable Output Data (GPIO Bank3, EMIO, Lower 16bits)
REG_MASK_DATA_3_MSW0x1c32Maskable Output Data (GPIO Bank3, EMIO, Upper 16bits)
REG_DATA_00x4032Output Data (GPIO Bank0, MIO)
REG_DATA_10x4432Output Data (GPIO Bank1, MIO)
REG_DATA_20x4832Output Data (GPIO Bank2, EMIO)
REG_DATA_30x4c32Output Data (GPIO Bank3, EMIO)
REG_DIRM_00x20432Direction mode (GPIO Bank0,MIO)
REG_OEN_00x20832Output enable (GPIO Bank0,MIO)
REG_INT_MASK_00x20c32Interrupt Mask Status (GPIO Bank0, MIO)
REG_INT_EN_00x21032Interrupt Enable/Unmask (GPIO Bank0, MIO)
REG_INT_DIS_00x21432Interrupt Disable/Mask (GPIO Bank0, MIO)
REG_INT_STAT_00x21832Interrupt Status (GPIO Bank0, MIO)
REG_INT_TYPE_00x21c32Interrupt Type (GPIO Bank0, MIO)
REG_INT_POLARITY_00x22032Interrupt Polarity (GPIO Bank0, MIO)
REG_INT_ANY_00x22432Interrupt Any Edge Sensitive (GPIO Bank0, MIO)
REG_DIRM_10x24432Direction mode (GPIO Bank1, MIO)
REG_OEN_10x24832Output enable (GPIO Bank1, MIO)
REG_INT_MASK_10x24c32Interrupt Mask Status (GPIO Bank1, MIO)
REG_INT_EN_10x25032Interrupt Enable/Unmask (GPIO Bank1, MIO)
REG_INT_DIS_10x25432Interrupt Disable/Mask (GPIO Bank1, MIO)
REG_INT_STAT_10x25832Interrupt Status (GPIO Bank1, MIO)
REG_INT_TYPE_10x25c32Interrupt Type (GPIO Bank1, MIO)
REG_INT_POLARITY_10x26032Interrupt Polarity (GPIO Bank1, MIO)
REG_INT_ANY_10x26432Interrupt Any Edge Sensitive (GPIO Bank1, MIO)
REG_DIRM_20x28432Direction mode (GPIO Bank2, EMIO)
REG_OEN_20x28832Output enable (GPIO Bank2, EMIO)
REG_INT_MASK_20x28c32Interrupt Mask Status (GPIO Bank2, EMIO)
REG_INT_EN_20x29032Interrupt Enable/Unmask (GPIO Bank2, EMIO)
REG_INT_DIS_20x29432Interrupt Disable/Mask (GPIO Bank2, EMIO)
REG_INT_STAT_20x29832Interrupt Status (GPIO Bank2, EMIO)
REG_INT_TYPE_20x29c32Interrupt Type (GPIO Bank2, EMIO)
REG_INT_POLARITY_20x2a032Interrupt Polarity (GPIO Bank2, EMIO)
REG_INT_ANY_20x2a432Interrupt Any Edge Sensitive (GPIO Bank2, EMIO)
REG_DIRM_30x2c432Direction mode (GPIO Bank3, EMIO)
REG_OEN_30x2c832Output enable (GPIO Bank3, EMIO)
REG_INT_MASK_30x2cc32Interrupt Mask Status (GPIO Bank3, EMIO)
REG_INT_EN_30x2d032Interrupt Enable/Unmask (GPIO Bank3, EMIO)
REG_INT_DIS_30x2d432Interrupt Disable/Mask (GPIO Bank3, EMIO)
REG_INT_STAT_30x2d832Interrupt Status (GPIO Bank3, EMIO)
REG_INT_TYPE_30x2dc32Interrupt Type (GPIO Bank3, EMIO)
REG_INT_POLARITY_30x2e032Interrupt Polarity (GPIO Bank3, EMIO)
REG_INT_ANY_30x2e432Interrupt Any Edge Sensitive (GPIO Bank3, EMIO)



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 4: Publicly available platforms using peripheral 'zynq_7000-gpio'

Platform NameVendor
Zynq_PSxilinx.ovpworld.org



XilinxPeripherals
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