LIBRARY  |  COMPANIES |   PLATFORMS |   PROCESSORS |   PERIPHERALS
XilinxZynq_7000Sdio



OVP Peripheral Model: XilinxZynq_7000Sdio



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

Zynq 7000 SD/SDIO Registers

Licensing

Open Source Apache 2.0

Limitations

This model implements the full set of registers but no behavior.

Reference

Zynq-7000 TRM (https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf)

Location

The zynq_7000-sdio peripheral model is located in an Imperas/OVP installation at the VLNV: xilinx.ovpworld.org / peripheral / zynq_7000-sdio / 1.0.



Net Ports

This model has the following net ports:

Table : Net Ports

NameTypeMust Be ConnectedDescription
intOutoutputF (False)Interrupt signal



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 1: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x1000T (True)

Table 2: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_SDMA_system_address_register0x032System DMA Address Register
ab_Block_Size_Block_Count0x432Block size register / Block count register
ab_Argument0x832Argument register
ab_Transfer_Mode_Command0xc32Transfer mode register / Command register
ab_Response00x1032Response register
ab_Response10x1432Response register
ab_Response20x1832Response register
ab_Response30x1c32Response register
ab_Buffer_Data_Port0x2032Buffer data port register
ab_Present_State0x2432Present State register
ab_Host_Power_Block_Gap_Wakeup_control0x2832(Host_control_Power_control_Block_Gap_Control_Wakeup_control) Host control register / Power control register / Block gap control register / Wake-up control register
ab_Clock_Timeout_control_Software_reset0x2c32(Clock_Control_Timeout_control_Software_reset) Clock Control register / Timeout control register / Software reset register
ab_Interrupt_status0x3032(Normal_interrupt_status_Error_interrupt_status) Normal interrupt status register / Error interrupt status register
ab_Interrupt_status_enable0x3432(Normal_interrupt_status_enable_Error_interrupt_status_enable) Normal interrupt status enable register / Error interrupt status enable register
ab_Interrupt_signal_enable0x3832(Normal_interrupt_signal_enable_Error_interrupt_signal_enable) Normal interrupt signal enable register / Error interrupt signal enable register
ab_Auto_CMD12_error_status0x3c32Auto CMD12 error status register
ab_Capabilities0x4032Capabilities register
ab_Maximum_current_capabilities0x4832Maximum current capabilities register
ab_Force_event0x5032(Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status) Force event register for Auto CMD12 error status register / Force event register for error interrupt status
ab_ADMA_error_status0x5432ADMA error status register
ab_ADMA_system_address0x5832ADMA system address register
ab_Boot_Timeout_control0x6032Boot Timeout control register
ab_Debug_Selection0x6432Debug Selection Register
ab_SPI_interrupt_support0xf032SPI interrupt support register
ab_Slot_status_Host_version0xfc32(Slot_interrupt_status_Host_controller_version) Slot interrupt status register and Host controller version register



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 3: Publicly available platforms using peripheral 'zynq_7000-sdio'

Platform NameVendor
Zynq_PSxilinx.ovpworld.org



XilinxPeripherals
Page was generated in 0.0238 seconds