This page provides information about the files and models that are in the that are specific to OpenHW Group cores/processors.

If you are a collaborator working with OpenHW and need access to run the reference model included with the OpenHW GitHub repository (AND NEED A LICENSE) please visit this page: OpenHWcollaboratorsPage.

If you are not a collaborator and want a license key to use the OpenHW Imperas reference model, then please contact for a key.

You do not need to download a copy of OVPsim to use the OpenHW UVM testbench as the OpenHW GitHub repository includes an Imperas reference model simulation (and just needs a key, visit here: OpenHWcollaboratorsPage).

If you want to be a collaborator - please contact OpenHW directly:

Imperas works with "OpenHW" Group on their verification for their 32 bit and 64 bit RISC-V open source processor cores. Currently this is working and available for CV32E40P as a UVM environment. Please visit the OpenHW project pages, and the UVM testbench GitHub repository

Imperas OVP Golden Reference Model and Step and Compare Testbench

The OpenHW SystemVerilog UVM testbench uses the Imperas OVP model of the CV32E40P as the golden reference and runs the model in a step and compare methodology. This means that the same program is loaded into both the RTL and the Imperas OVP golden reference model and they are then stepped instruction by instruction by the testbench and at every instruction retire the internal state is compared.

This means that it is hard for bugs to hide ensuring that the RTL is of the highest quality and conforms to the details of the RISC-V specification.


Getting licenses
If you are a collaborator with OpenHW please contact them to set you up with license key access:
If you are a collaborator please visit this page to get a license key: OpenHWcollaboratorsPage.

As Imperas / OVP release models of OpenHW components, they will get listed here.

The following 1 pages belong to OpenHWpage:


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